ENSIMAG

M
éthodologie de Conception SoCs
Méthodologie
M
éthodologie de conception SystemC
Méthodologie

Présenté par

Prof. Nacer-Eddine ZERGAINOH, Ph.D

Laboratoire TIMA
Tel. +33 476 574 652
Fax.+33 476 473 814
Email: Nacer-Eddine.Zergainoh@imag.fr
46, av. Félix Viallet - 38031 Grenoble Cedex France

Polytech
Grenoble

Learning Objectives of Chapiter 1


This chapter provides background and general overview of modeling
with SystemC



Learning Objectives
g

Understand why C++ is inadequate and in general how
SystemC addresses these inadequacies.

g

Understand modeling terms and model types used in
SystemC.

g

Understand at a high level how SystemC systems and
modules are put together.

g

Understand at a high level how SystemC modules
communication paradigm.

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Méthodologie de conception de Systèmes Monopuces

1

General Overview


Why C++ is Inadequate
g
g

C++ is certainly adequate for modeling the software components of a system.
There are three major reasons why C++ is inadequate for modeling the hardware
components:
Notion of Time, Concurrency, Hardware date types.
Notion of Time
C++ does not support the notion of time sequenced events, there is no
notion of time.
In systemC, notion of time is introduced and Implemented.
Concurrency
C++ does not support the idea of concurrency.
Hardware systems are inherently concurrent. They operate in parallel
In SystemC, processes are defined which are executed in parallel within the
simulator.
Hardware data types
C++ native data
sequenced events, there is no notion of time.
SystemC consists of a C++ class library and simulation kernel that addresses
these inadequacies.
SystemC "extends" the language without changing the syntax by using classes.
Modules are introduced as a means of encapsulating behavior and describing
hierarchy.


g





g







g





g

g
g

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Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
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Méthodologie de conception de Systèmes Monopuces

2

Augmenter le niveau d ’abstraction
50k SLDL
Transactions

System-level specification

Architecture exploration

Abstract SW
(SystemC, C, C++)

HW Behavior
(VHDL, SystemC)

Software Targeting
&
Processor Selection

Hardware
Synthesis

HW/SW Interfaces
Synthesis
Processor

Interfaces

150k VHDL /C
computation steps

350k Synt. RTL /Exec. C
clock cycles
HW

1000k Gates/Instr
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Méthodologie de conception de Systèmes Monopuces

Answer is in C/C++


Global Language
Customer-System Architect-Hardware/Software designer
Easy to Write & Debug algorithm
Numerous algorithms written in C/C++



C interface to HDL
FLI/PLI “It’s already standard !”
Real-Stimuli/Test Automation enhance IP quality greatly



Designing in one-language
From System to IP / From Idea to Chip
Hardware modeling & Software development tools



C/C++ Based Design tools





Hardware Modeling with C/C++ “SystemC”
In-System C model emulator “Dynalith’ iSAVE”
C-to-HDL Translators “C-Level Design”
C Model Synthesizers “Synopsys Co-Centric”

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Méthodologie de conception de Systèmes Monopuces

3

C/C++ : From Idea to Chip
idea

C-Libraries
C/C++ Environment
(SystemC )

C/C++ Algorithmic Model
H/W-S/W Design Partition

S/W Debugging

H/W Verification

Algorithm

Timed C
Model
HDL S/W Dev
Model Tools

C/C++ System
Model
System
Simulation

BCA

Executable Refined
Develop Software Spec.

Reusable IP

Structural C
Model

HDL

Result

Real-Stimuli

Merge S/W-H/W

Simulation
SoC
BCA : Bus Cycle Accuracy Model

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Méthodologie de conception de Systèmes Monopuces

VSIA SLD
Data Types
Spec (draft)

SystemC History
Synopsys

Synopsys

ATG

“Scenic”

UC
Irvine
1996

Synopsys

SystemC
v0.90
Sep. 99

“Fridge”

Frontier Design
A/RT Library
1991
imec
1992

CoWare
“N2C”
1997

System-Level Modeling:Methodo.
Computing Models, Comm. & Synch
Hw/Sw codesign …
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Fixed Point
Types

SystemC
v1.0
Apr. 00

Abstract
Protocols

SystemC
2.0

SystemC
v1.1
Jun. 00
2001

Méthodologie de conception de Systèmes Monopuces

4

SystemC Methodology
SystemC Model

- Refinement Methodology
: Not convert C to HDL for timing constructs
Simulation

- Written in Single Language from System to RTL model
- Less effort to convert Synthesizable HDL

Refinement

Synthesis

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Méthodologie de conception de Systèmes Monopuces

SystemC methodology versus standard

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Méthodologie de conception de Systèmes Monopuces

5

SystemC Design Methodology (cont’d)


Advantages
g

Refinement methodology

g

Written in a single language

g

Higher productivity

g

Reusable testbenches

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Méthodologie de conception de Systèmes Monopuces

SystemC design Methodology

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Méthodologie de conception de Systèmes Monopuces

6

Mixed level simulation

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Méthodologie de conception de Systèmes Monopuces

SystemC 2.0 is …
C++

Class Library use for

g

Cycle-Accurate model for Software Algorithm

g

Hardware Architecture

g

Interface of SoC (System-on-Chip)

g

System-level designs

g

Executable Specification

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Méthodologie de conception de Systèmes Monopuces

7

SystemC class library

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Méthodologie de conception de Systèmes Monopuces

SystemC and User Module
User
User
Module
Module
#1
#1

User
User
Module
Module
#2
#2

.....

User
User
Module
Module
#N
#N

Event & Signal I/F
C++ Class Library
Events
Hardware Simulation Kernel
(Event Scheduler)

SystemC
SystemC
Executable Specification
Executable Specification
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Méthodologie de conception de Systèmes Monopuces

8

SystemC (1)


Support Hardware-Software Co-Design



Interface in a C++ environment
g

Modules
Container class includes hierarchical Entity and Processes
Processes
Describe functionality, Event sensitivity
Ports
Single-directional(in, out), Bi-directional(inout) mode
Signals
Resolved, Unresolved signals
Rich set of port and signal types


g



g



g



g
g

Rich set of data types
All C/C++ types, 32/64-bit signed/unsigned, fixed-points, MVL,
user defined


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Méthodologie de conception de Systèmes Monopuces

SystemC (2)


Interface in a C++ environment (continued)

g

Clocks
Special signal, Timekeeper of simulation and Multiple clocks, with
arbitrary phase relationship
Cycle-based simulation
High-Speed Cycle-Based simulation kernel
Multiple abstraction levels
Un-timed from high-level functional model to detailed clock cycle
accuracy RTL model
Communication Protocols

g

Debugging Supports

g

Run-Time error check
Waveform Tracing
Supports VCD, WIF, ISBD

g



g



g







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Méthodologie de conception de Systèmes Monopuces

9

SystemC 2.0 Language Architecture
Standard Channels
for Various MOC’s
Kahn Process Networks,
Static Dataflow, etc.

Methodology-Specific
Channels
Master/Slave Library, etc.

Elementary Channels
Signal, Timer, Mutex, Semaphore, Fifo, etc.
Data Types

Core Language
Modules
Ports
Processes
Interfaces
Channels
Events

Logic Type (0’XZ)
Logic Vectors
Bits and Bit Vectors
Fixed Point Numbers
C++ Built-In Types
(int, char,double,etc.)
C++ user-defined types

C++ Language Standard
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Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
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Méthodologie de conception de Systèmes Monopuces

10

Module


Module
g

Basic building block of design partitioned
C++ Class, similar to “entity”(VHDL) or “module”(Verilog)

g

Properties

g





g

Break complex systems into smaller more manageable pieces
Hide internal data representation and algorithms from other
modules

Declaration
SC_MODULE(module_name){
Module contains some elements
Ports
Local signals
process
process
Local data
Other modules
module
module
Processes
Constructors


g



module





process
process





module
module



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Méthodologie de conception de Systèmes Monopuces

Module


Module
SC_MODULE(module_name)
{
// Declare Module Ports
// Declare Module Signals, Member functions
// Module Construct : SC_CTOR
// Process Construct and Sensitize to signal:
//
SC_METHOD, SC_THREAD, SC_CTHREAD
// Sub-Module Instantiate and Port Mapping
// Initialize of Module Signals
}

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11

Module Ports
Pass

data to or from processes of a module

g

Input port
sc_in<type> port_name;

g

Output port
sc_out<type> out_port_name;

g

Bi-Directional port
sc_inout<type> inout_port_name;

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Méthodologie de conception de Systèmes Monopuces

Module Signals
Local

to a Module

Used

to connect ports of sub-modules

sc_signal<type> signal_name;

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12

Internal Data Storage
Local

variable

Cannot

be used to connect ports

Storage

types

g

C++ type

g

SystemC type

g

User defined type

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Méthodologie de conception de Systèmes Monopuces

Module Constructor




Similar to “architecture” or module body
Processes and/or Sub-module instantiated
“module_name” passed when instantiated to identify the module

SC_MODULE(module_name)
{
…………

SC_CTOR(module_name) // Create Module
{
// Processes and Sensitize
// Sub-Module Instantiate
//Initialize Local signals and Internal
storage
}
}

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13

Sub-Module Instantiate


Module Instantiate
module_type Inst_module (“label”);



Module Instantiate as pointer
module_type *pInst_module;
// Instanciate in the Module constructor SC_CTOR

pInst_module = new module_type(“label”);

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Méthodologie de conception de Systèmes Monopuces

Sub-Module Port Mapping


Positional Port Mapping
Inst_module << s << c << q;
(*pInst_module)(s,c,q);



Named Port Mapping
Inst_module.a(s);
Inst_module.b(c);
Inst_module.q(q);
pInst_module -> a(s);
pInst_module -> b(c);
pInst_module -> q(q);

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14

Hierarchy of Modules
SC_MODULE(filter)
{
// Sub-modules : “component”

sample *s1;
coeff *c1;
mult *m1;
sc_signal<sc_uint 32> q, s, c; // Signals

q
sample
din

dout

s

// Module constructor : “architecture” body

SC_CTOR(filter)
{
// Instantiate Sub-Modules and Port mapping

mult
s1
a
q
coeff

b

s1 = new sample (“s1”);
s1->din(q); // Named Mapping
s1->dout(s);

m1

cout c

c1

c1 = new coeff(“c1”);
c1->out(c);

filter
filter

m1 = new mult (“m1”);
(*m1)(s, c, q); //Positional Mapping
}
}
INPG/ENSERG

Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
INPG/ENSERG

Méthodologie de conception de Systèmes Monopuces

15

Processes


Member function of SC_MODULE



Provides functionality of Module



Identify to SystemC kernel (Simulator)



Call and Execute : “Sensitive to”



Type of Processes (execute method)
g

Method : SC_METHOD

g

Thread : SC_THREAD

g

Clocked Thread : SC_CTHREAD

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Méthodologie de conception de Systèmes Monopuces

Process and “Sensitize to”


System C

#include “systemc.h”
SC_MODULE(dff) {
sc_in<bool>
din;
sc_in<bool>
clock;
sc_out<bool> dout;
void doit(); // Member function



VHDL

entity dff is
port ( din, clock : in bit;
dout : out bit );
end dff;
architecture dff of dff is
begin

SC_CTOR(dff) {
SC_METHOD(doit); // Process
sensitive_pos << clock; //
Sensitize to
}

doit : process(clock) –
Sensitivity List
begin

if (clock’
(clock’event and
clock=‘
clock=‘1’) then

};
void dff::doit() { // Member function
as Process body
dout = din;
}

INPG/ENSERG

dout <= din;
end if;
end process;
end dff;

Méthodologie de conception de Systèmes Monopuces

16

Initialize Module


When a Module instantiated,
g
g

Module name passed to identify module
Module Constructor creates and initializes this Module

SC_MODULE(ram) {
sc_in<int> addr; // Input port
sc_in<int> datain; // Input port
sc_in<bool> rwb; // Input port
sc_out<int> dout; // Output port
int memdata[64]; // Local memory storage, Created when instantiated
int i;
void ramread();
void ramwrite();
SC_CTOR(ram) {
SC_METHOD(ramread) // Memory Read Process
sensitive << addr << rwb;
SC_METHOD(ramwrite) // Memory Write Process
sensitive << addr << datain << rwb;
for (i=0; i++; i<64)
instantiated
memdata[i] = 0;

// Initialize Local Storage when

}
}
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Méthodologie de conception de Systèmes Monopuces

Process


Basic Unit of Parallel Execution



Behave like Function (SC_METHOD)





g

Sequential in the Process

g

Returns execution back to calling mechanism

Execute Concurrently
g

Processes are NOT Hierarchical.

g

Processes have Sensitive List.

g

Processes are triggered (called) by EVENT on Sensitivity List.

Difficulties of Doing Parallelism
g



Electronic system modeling with Sequential Programming Language

Types of Processes
g

Method : SC_METHOD

g

Thread : SC_THREAD

g

Clocked Thread : SC_CTHREAD
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Méthodologie de conception de Systèmes Monopuces

17

Processes


Only thing in SystemC that actually does anything



Procedural code with the ability to suspend and
resume



Methods of each module class



Like Verilog’s initial blocks

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Méthodologie de conception de Systèmes Monopuces

Three Types of Processes



METHOD
g



THREAD
g



Models combinational logic

Models testbenches

CTHREAD
g

Models synchronous FSMs

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Méthodologie de conception de Systèmes Monopuces

18

METHOD Processes


Triggered in response to changes on inputs



Cannot store control state between invocations



Designed to model blocks of combinational logic

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Méthodologie de conception de Systèmes Monopuces

METHOD Processes
Process is simply a
method of this class

SC_MODULE(onemethod) {
sc_in<bool> in;
sc_out<bool> out;
void inverter();

Instance of this
process created

SC_CTOR(onemethod) {
SC_METHOD(inverter);
sensitive(in);

and made sensitive
to an input

}
};
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Méthodologie de conception de Systèmes Monopuces

19

METHOD Processes


Invoked once every time input “in” changes



Should not save state between invocations



Runs to completion: should not contain infinite loops
g

Not preempted

void onemethod::inverter() {
bool internal;
internal = in;
out = ~internal;
}
INPG/ENSERG

Read a value from the port
Write a value to an
output port

Méthodologie de conception de Systèmes Monopuces

THREAD Processes


Triggered in response to changes on inputs



Can suspend itself and be reactivated



g

Method calls wait to relinquish control

g

Scheduler runs it again later

Designed to model just about anything

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Méthodologie de conception de Systèmes Monopuces

20

THREAD Processes
SC_MODULE(onemethod) {
sc_in<bool> in;
sc_out<bool> out;

Process is simply a
method of this class

void toggler();
SC_CTOR(onemethod) {
Instance of this
process created

SC_THREAD(toggler);
sensitive << in;

alternate sensitivity
list notation

}
};

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Méthodologie de conception de Systèmes Monopuces

THREAD Processes


Réveiller a chaque fois qu’un “input” change



State saved between invocations



Infinite loops should contain a wait()

void onemethod::toggler() {
bool last = false;
for (;;) {
last = in; out = last; wait();
last = ~in; out = last; wait();
}
}
INPG/ENSERG

Relinquish (abandonner)
control until the next
change of a signal on the
sensitivity list for this
process

Méthodologie de conception de Systèmes Monopuces

21

CTHREAD Processes


Triggered in response to a single clock edge



Can suspend itself and be reactivated



g

Method calls wait to relinquish control

g

Scheduler runs it again later

Designed to model clocked digital hardware

INPG/ENSERG

Méthodologie de conception de Systèmes Monopuces

CTHREAD Processes
SC_MODULE(onemethod) {
sc_in_clk clock;
sc_in<bool> trigger, in;
sc_out<bool> out;

Instance of this
process created and
relevant clock edge
assigned

void toggler();
SC_CTOR(onemethod) {
SC_CTHREAD(toggler, clock.pos());
}
};
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Méthodologie de conception de Systèmes Monopuces

22

CTHREAD Processes
Reawakened at the edge of the clock
State saved between invocations
Infinite loops should contain a wait() Relinquish control
until the next clock
cycle in which the
void onemethod::toggler() {
trigger input is 1
bool last = false;
for (;;) {
wait_until(trigger.delayed() == true);
last = in; out = last; wait();
last = ~in; out = last; wait();
Relinquish control
until the next clock
}
cycle
}




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Méthodologie de conception de Systèmes Monopuces

Processes, Type of
SC_METHOD

Process Type

SC_THREAD

SC_CTHREAD

Exec. Trigger

Signal Events

Signal Events

Clock Edge

Exec. Suspend

NO

YES

YES

Infinite Loop

NO

YES

YES

Suspend /
Resume by

N.A.

wait()

wait()

Construct &

SC_METHOD(call_back);

SC_THREAD(call_back);

Sensitize

sensitive(signals);

sensitive(signals);

sensitive_pos(signals);

sensitive_pos(signals);

sensitive_neg(signals);

sensitive_neg(signals);

Method

wait_until()

INPG/ENSERG

SC_CTHREAD(call_back,clo
ck.pos() );
SC_CTHREAD(call_back,clo
ck.neg());

Méthodologie de conception de Systèmes Monopuces

23

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
INPG/ENSERG

Méthodologie de conception de Systèmes Monopuces

Ports


External interface of Module



Port Modes



g

Input
sc_in<port_type>

g

Output
sc_out<port_type>

g

Inout
sc_inout<port_type>

Scalar Port
sc_in<sc_uint<32> > a;



Vector (Array) Port
sc_out<sc_logic> a[32];
INPG/ENSERG

// 32-bit unsigned integer

// Create Ports a[0] to a[31]
Méthodologie de conception de Systèmes Monopuces

24

Signals


Global/Static in the module



Bounded to the module



Declaration

sc_signal<signal_type>


Scalar Signal

sc_signal<sc_uint<32 > > a;


Vector Signal

sc_signal<sc_logic> a[32];

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Méthodologie de conception de Systèmes Monopuces

Ports and Signals


Differed assign same as VHDL/Verilog



Types of Ports and Signals
g

All C/C++ native types

g

SystemC types

g



Signed/Unsigned integer types



Two valued(0,1)/Multi-valued(0,1,Z,X) logic types



Scalar and Vector types



Fixed-point types

User defined types

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Méthodologie de conception de Systèmes Monopuces

25

Resolved/Unresolved


SystemC support resolved Ports and Signals



Resolved Port/Signal



g

Multi-Valued Logic type : 0, 1, Z, X

g

Allow Multiple Drive

Resolved Vector Port

sc_in_rv<n> x; // n bits wide resolved input


Resolved Vector Signal

sc_signal_rv<n> x; // n bits wide resolved

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Méthodologie de conception de Systèmes Monopuces

Signal Binding


Binding port and/or signal with same type



Port is bound to a single signal



Port to port binding directly

PCI
FIFO
data

din
No signal
required

u_FIFO

u_PCI

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Méthodologie de conception de Systèmes Monopuces

26

Clocks


Special Object



Create clock
sc_clock clock_name (
“clock_label”, period, duty_ratio, offset, first_value );



Clock Binding

f1.clk( clk.signal() );


Clock Waveform Example

sc_clock clock1 ("clock1", 20, 0.5, 2, true);
20

2

INPG/ENSERG

12

22

32

42

Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
INPG/ENSERG

Méthodologie de conception de Systèmes Monopuces

27

Data Types




SystemC supports
g

Native C/C++ Types

g

SystemC Types

SystemC Types
g

Data type for system modeling

g

2 value (‘0’,’1’) logic/logic vector

g

4 value (‘0’,’1’,’Z’,’X’) logic/logic vector

g

Arbitrary sized integer (Signed/Unsigned)

g

Fixed Point types (Templated/Untemplated)

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Méthodologie de conception de Systèmes Monopuces

SystemC Types
Type

Description

sc_bit

2 value single bit

sc_logic

4 value single bit

sc_int

1 to 64 bit signed integer

sc_uint

1 to 64 bit unsigned integer

sc_bigint

arbitrary sized signed integer

sc_biguint

arbitrary sized unsigned integer

sc_bv

arbitrary sized 2 value vector

sc_lv

arbitrary sized 4 value vector

sc_fixed

templated signed fixed point

sc_ufixed

templated unsigned fixed point

sc_fix

untemplated signed fixed point

sc_ufix

untemplated unsigned fixed point

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Méthodologie de conception de Systèmes Monopuces

28

Type sc_bit, sc_logic


sc_bit
g
g
g



sc_logic
g
g
g



2 valued single bit – {‘0’ (false), ‘1’ (true)}
Use character literal for assignment operation
Use C++ bool type for equality operation
4 valued single bit
‘0’(false), ‘1’(true), ‘X’(unknown), ‘Z’(hi-imp/floating)
Use character literal for assignment operation

Mixed use of operand type of sc_bit and sc_logic

Operators
Bitwise

& (and)

| (or)

^ (xor)

~ (not)

Assignment

=

&=

|=

^=

Equality

==

!=

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Méthodologie de conception de Systèmes Monopuces

Type sc_logic


4 valued single bit
g

‘0’(false), ‘1’(true), ‘X’(unknown), ‘Z’(hi-imp/floating)

g

Use character literal for assignment operation

g

Mixed use of operand type of sc_bit

“sc_logic” Operators
Bitwise

& (and)

| (or)

^ (xor)

~ (not)

Assignment

=

&=

|=

^=

Equality

==

!=

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29

Fixed Precision
Unsigned and Signed Integers




C++ “int” type
g

C/C++ native type

g

Use C/C++ native type for fast simulation

1 to 64 bit integer
sc_int<n>
sc_uint<n>
g



Mixed use of operand type of C++ integer type

Truncate and/or Sign extend when mis-matched assignment of size

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Méthodologie de conception de Systèmes Monopuces

Fixed Precision Integer Operators

Fixed Precision integer Operators
Bitwise

~

&

|

^

>>

Arithmetic

+

-

*

/

%

Assignment

=

+=

-=

*=

/=

Equality

==

!=

Relational

<

<=

>

>=

Auto-Inc/Dec

++

--

Bit Select

[x]

ex) mybit = myint[7]

Part Select

range()

ex) myrange = myint.range(7,4)

Concatenation

(,)

ex) intc = (inta, intb);

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<<

%=

&=

|=

^=

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30

Arbitrary Precision Signed/Unsigned Integer

Type


Larger than 64 bit integer
g

sc_bigint<n>

g

sc_biguint<n>



2’s complement arithmetic operations



Greater precision, Slower speed



Mixed use of operand types with
g

C++ integer

g

sc_int

g

sc_uint

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Méthodologie de conception de Systèmes Monopuces

Arbitrary Precision Integer Operators

Arbitrary Precision Integer Operators
Bitwise

~

&

|

^

>>

Arithmetic

+

-

*

/

%

Assignment

=

+=

-=

*=

/=

Equality

==

!=

Relational

<

<=

>

>=

Auto-Inc/Dec

++

--

Bit Select

[x]

ex) mybit = myint[7]

Part Select

range()

ex) myrange = myint.range(7,4)

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<<

%=

&=

|=

^=

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31

Arbitrary Length : Bit / logic Vector






Bit Vector
g

sc_bv<n>

g

2 valued (bit) arbitrary length vector

g

No arithmetic operation

g

Faster simulation than the “sc_lv” type

Logic Vector
g

sc_lv<n>

g

4 valued (logic) arbitrary length vector

Assignment “=“ Operator
g

String Literal for vector constant assignment

g

Convert logic vector to integer (int or uint)

g

Assignment between “sc_bv” and “sc_lv”

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Méthodologie de conception de Systèmes Monopuces

Arbitrary Length: Vector Operators
Arbitrary Length Vector Operators
Bitwise

~

&

|

^

>>

<<

Assignment

=

+=

-=

*=

/=

%=

Equality

==

!=

Bit Select

[x]

Part Select

range()

Concatenation

(,)

Reduction

and_reduction() or_reduction() xor_reduction()

Convert

to_string()

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&=

|=

^=

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32

User Defined Type Issues


Comparison Operator
g

Built-in comparison “==“ operator CANNOT be used

g

Provide inline function for user defined types

inline bool operator == (const packet_type& rhs) const
{
return (rhs.info==info && rhs.seq==seq && rhs.retry==retry);
}



Tracing a User Defined Type
g

Waveform tracing support VCD, WIF, ISDB format

g

Implement sc_trace() function for user defined types

void sc_trace(sc_trace_file* tf, const packet_type& v, const sc_string&
NAME)
{
sc_trace(tf, v.info, NAME+”.info”);
sc_trace(tf, v.seq, NAME+”.seq”);
sc_trace(tf, v.retry, NAME+”.retry”);
}
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Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
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33

Communication and Synchronization


SystemC 1.0 Modules and Processes are still useful in
system design



But communication and synchronization mechanisms in
SystemC 1.0 (Signals) are restrictive for system-level
modeling
g

Communication using queues

g

Synchronization (access to shared data) using mutexes

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Communication and Synchronization


SystemC 2.0 introduces general-purpose
g

Channels
A container class for communication and
synchronization
They implement one or more interfaces
Interfaces
Specify a set of access methods to the channel
Events
Flexible, low-level synchronization primitive
Used to construct other forms of synchronization




g



g





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34

Communication and Synchronization


Other comm & sync models can be built based on the
above primitives
g

Examples








HW-signals,
queues (FIFO, LIFO, message queues, etc)
semaphores,
memories and busses (both at RTL and transaction-based
models)

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Example


Design a FIFO of 8 characters, along with a producer and a
consumer process, communicating through the FIFO

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35

Communication and Synchronization:
abstract channel
Interfaces
Module1

Module2
Channel

Events
Ports to Interfaces

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A Communication Modeling Example:
FIFO

Write Interface
Producer

Consumer
FIFO

Read Interface

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36

FIFO Example:Declaration of Interfaces
p

c

FIFO

class write_if : public sc_interface
{
public:
virtual void write(char) = 0;
virtual void reset() = 0;
};
class read_if : public sc_interface
{
public:
virtual void read(char&) = 0;
virtual int num_available() = 0;
};

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FIFO Example:Declaration of FIFO channel
p

class fifo: public sc_channel,
public write_if,
public read_if

FIFO

c

void write(char c) {
if (fifo_full())
wait(read_event);

{
private:
enum e {max_elements=10};
char data[max_elements];
int num_elements, first;
sc_event write_event,
read_event;
bool fifo_empty() {…};
bool fifo_full() {…};

data[ <you calculate> ] = c;
++num_elements;
write_event.notify();
}
void read(char &c) {
if (fifo_empty())
wait(write_event);
c = data[first];
--num_elements;
first = …;
read_event.notify();

public:
fifo() : num_elements(0),
first(0);
}
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37

Declaration of FIFO channel (cont’d)
p

FIFO

c

void reset() {
num_elements = first = 0;
}
int num_available() {
return num_elements;
}
}; // end of class declarations

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FIFO Example
Any

channel must

g

be derived from sc_channel class

g

be derived from one (or more) classes
derived from sc_interface

g

provide implementations for all pure virtual
functions defined in its parent interfaces

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38

FIFO Example
Note the following extensions beyond SystemC 1.0



g

wait() call
wait(sc_event) => dynamic sensitivity
wait(time)
wait(time_out, sc_event)
Events
are the fundamental synchronization primitive
have no type, no value
always cause sensitive processes to be resumed
can be specified to occur:
– immediately/ one delta-step later/ some specific time later






g









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Méthodologie de conception de Systèmes Monopuces

Completing the Comm. Modeling Example
p
SC_MODULE(producer) {
public:
sc_port<write_if> out;

FIFO

SC_MODULE(consumer) {
public:
sc_port<read_if> in;

SC_CTOR(producer) {
SC_THREAD(main);
}

SC_CTOR(consumer) {
SC_THREAD(main);
}

void main() {
char c;
while (true) {
out.write(c);
if(…)
out.reset();
}
}

void main() {
char c;
while (true) {
in.read(c);
cout<<

};

c

in.num_available(); }
}
};

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39

Completing the Comm. Modeling Example
p

FIFO

c

SC_MODULE(top) {
public:
fifo afifo;
producer *pproducer;
consumer *pconsumer;
SC_CTOR(top) {
pproducer=new producer(“Producer”);
pproducer->out(afifo);
pconsumer=new consumer(“Consumer”);
pconsumer->in(afifo);
};

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Méthodologie de conception de Systèmes Monopuces

Completing the Comm. Modeling Example


Note:
g

Producer module


g

sc_port<write_if> out;

– Producer can only call member functions of write_if interface
Consumer module
sc_port<read_if> in;


g

– Consumer can only call member functions of read_if interface
Producer and consumer are

g

unaware of how the channel works
just aware of their respective interfaces
Channel implementation is hidden from communicating modules




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40

Completing the Comm. Modeling Example


Advantages of separating communication from
functionality
g

Trying different communication modules

g

Refine the FIFO into a software implementation

g

Using queuing mechanisms of the underlying RTOS
Refine the FIFO into a hardware implementation




Channels can contain other channels and modules
– Instantiate the hw FIFO module within FIFO channel
– Implement read and write interface methods to properly
work with the hw FIFO
– Refine read and write interface methods by inlining them
into producer and consumer codes

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Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
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41

Models of Computation within SystemC


Many different models
g



The best choice is not always clear

Basic topics in a computation model
g

The model of time, and event ordering constraints
Time model: real valued, integer-valued, untimed
Event ordering: globally ordered, partially ordered
Supported methods of communication between concurrent
processes




g

g

Rules for process activation

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Méthodologie de conception de Systèmes Monopuces

Models of Computation within SystemC


SystemC 2.0
g

Generic model of computation

g

The designer is to implement his desired model
(Virtually) all discrete-time models are supported












Static Multi-rate Data-flow
Dynamic Multi-rate Data-flow
Kahn Process Networks
Communicating Sequential Processes
Discrete Event as used for
– RTL hardware modeling
– network modeling (e.g. stochastic or “waiting room” models)
– transaction-based SoC platform-modeling

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42

Models of Computation within SystemC


Proof of generic usage of SystemC 2.0 primitives
g



Signals are realized on top of channels, interfaces, and events

SystemC 2.0 is not suitable for continuous-time
models (e.g. analog modeling)

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Méthodologie de conception de Systèmes Monopuces

Plan du chapitre


Introduction



Modules and Hierarchy



Process



Ports and signals



Data types



Communication and synchronization



Computation models with systemC



Application examples
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43

SystemC descriptions


create modules and interconnect them.



run simulation



trace signals to monitor

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SystemC Module descriptions


Module Header File
g

Each module header file contains:
Port declarations, Internal signal variable declarations, Internal data
variable declarations,
Process declarations, Member function declarations,
Module constructor








Syntax
#include "systemc.h"
SC_MODULE (module_name) {
//Module port declarations and Signal variable declarations
//Data variable declarations
//Member function declarations and Method process declarations
//Module constructor
SC_CTOR (module_name) {
//Register processes
//Declare sensitivity list
}
}

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Constructor :
– it defines all operations to be done
when an object is created
– it initialize ports and data
– it create internal hierarchy of the
module

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44

SystemC Module descriptions


Instantiation = element creation
g

it automatically calls the module constructor,

g

Instanciation dans le “sc_main” could be done in the
following way :

Module_name inst1("inst1"); // statique
Or:
Module_name* inst1 = new module_name("inst1"); //dynamique

It calls constructor for inst1

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SystemC Module descriptions


Ports and signals
g

Ports connect to signals and have a data type associated with them.

g

Modules use ports to communicate with other modules.

g

In hierarchical modules, use signals to communicate between the ports
of instantiated modules.

g

Use internal signals for peer-to-peer communication between processes
within the same module.

g

There are :
hardware ports : sc_in<type>, sc_out<type>, sc_inout<type>, that are
to be connected at signals: sc_signal<type>.
special ports (sc_fifo_in<type>…) and
abstract ports for high level design






g

There are two ways to connect signals to ports in SystemC:
named mapping and positional mapping.


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45

SystemC module descriptions


Process and sensitivity list
g

Processes are functions that are identified to the SystemC kernel and
called whenever signals these processes are “sensitive to” change value.

g

A process contains a number of statements that implement the
functionality of the process.

g

These statements are executed sequentially until :
the end of the process occurs, or
the process is suspended by one of the wait function calls.






Example:
SC_MODULE(my_module){
// Ports
sc_in<int> a;
sc_in<bool> b;
sc_out<int> x;
sc_out<int> y;
sc_in<bool> clock;

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Méthodologie de conception de Systèmes Monopuces

SystemC module descriptions


Process and sensitivity list (cont.)
// Internal signals
sc_signal<bool>c;
sc_signal<int> d;
sc_signal<int> e;
// process declaration
void my_method_proc();
// module constructor
SC_CTOR(my_module) {
// register process
SC_METHOD(my_method_proc);
// declare level-sensitive sensitivity list
sensitive_pos (clock); //Function delaration
sensitive << a << c << d; // Stream declaration
sensitive(b); //Function declaration
sensitive(e); //Function declaration
}
};
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46

SystemC module descriptions


Implementing the Module
g

g



In the module implementation file (cpp file), define the functionality of
each SC_METHOD process and member function.
In the previous example, my_method_proc() will be implemented.

Reading and Writing Ports and Signals
g

In the module implementation description, you can read from or write to a
port or signal by using the read and write methods or by assignment.

g

When you read or write a port, as a recommended coding practice, use
the read() and write() methods. Use the assignment operator for
variables.
// read method
address = into.read(); // get address
// assignment
temp1 = address; // save address
data_tmp = memory[address]; // get data from memory
// write method
outof.write(data_tmp); // write out
// assignment
temp2 = data_tmp; // save data_tmp
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Méthodologie de conception de Systèmes Monopuces

SystemC module descriptions


Exemple 1 : “counter in SystemC”

//count.h
#include "systemc.h"
SC_MODULE(count) {
sc_in<bool> load;
sc_in<int> din; // input port
sc_in<bool> clock; // input port
sc_out<int> dout; // output port
int count_val; // internal data storage
void count_up();
SC_CTOR(count) {
SC_METHOD(count_up); // Method process
sensitive_pos << clock;
}
};

//count.cpp
#include "count.h"
void count::count_up() {
if (load) {
count_val = din;
} else
count_val = count_val + 1; // could also
dout = count_val;
}
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47

SystemC module descriptions




TestBenches
g

Testbenches are used to provide stimulus to a design under test and
check design results.

g

The testbench can be implemented in a number of ways.

g

The stimulus can be generated by one process and results checked by
another.

g

The stimulus can be embedded in the main program and results checked
in another process.

g

The checking can also be embedded in the main program, etc.

g

There is no clear "right" way to do a testbench, it is dependent on the
user application.

Example 2: “testbench for the counter”
// count_stim.h
#include "systemc.h"
SC_MODULE(count_stim) {
sc_out<bool> load;
sc_out<int> din; // input port
sc_in<bool> clock; // input port
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Méthodologie de conception de Systèmes Monopuces

sc_in<int> dout;
void stimgen();
SC_CTOR(count_stim) {
SC_THREAD(stimgen);
sensitive_pos (clock);
}
};
// count_stim.cpp
#include "count_stim.h"
void count_stim::stimgen() {
while (true) {
load = true; // load 0
din = 0;
wait(); // count up, value = 1
load = false;
wait(); // count up, value = 2
wait(); // count up, value = 3
wait(); // count up, value = 4
wait(); // count up, value = 5
wait(); // count up, value = 6
wait(); // count up, value = 7
}

- The testbench will drive the load and
din inputs of the count module.
- The clock input of the count module
and the clock input of the “count_stim”
module will be generated from a clock.

}
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48

SystemC module descriptions
Clocks : are special objects in SystemC. They generate timing signals
used to synchronize events in the simulation.



g

Clocks order events in time so that parallel events in hardware are
properly modeled by a simulator on a sequential computer.

g

A clock object has a number of data members to store clock settings, and
methods to perform clock actions. To create a clock object use the
following syntax:
sc_clock
clock1("clock1", 20, 0.5, 2, true);

g

This declaration will create a clock object named clock1 with a period of
20 time units, a duty cycle of 50%, the first edge will occur at 2 time units,
and the first value will be true.

g

All of these arguments have default values except for the clock name.


The period defaults to 1, the duty cycle to 0.5, the first edge to 0, and
the first value to true.

g

Typically clocks are created at the top level of the design in the testbench
and passed down through the module hierarchy to the rest of the design.

g

This allows areas of the design or the entire design to be synchronized
by the same clock.
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SystemC module descriptions


Example : In this example the top level routine sc_main instantiates a module called
filter and declares some local signals that will connect filter with other module
instantiations.
g

Function ck1.signal() is mapped to the clk port of the filter object.

g

The clock is named ck1 and the clock frequency is specified as 20 time units.

Every 20 time units the clock will make a complete transition from true to false and
back to true.
int sc_main(int argc, char*argv[]) {
g Notice that a clock signal is not declared :
g

sc_signal<int> val;
sc_signal<sc_logic> load;
sc_signal<sc_logic> reset;

g

instead a clock object is instantiated,

g

its parameters are setup,

and its signal method is used to provide
the clock signal.
g

sc_signal<int> result;
sc_clock ck1("ck1", 20, 0.5, 0, true);
filter f1("filter");
f1.clk(ck1.signal());
f1.val(val);
f1.load(load);
f1.reset(reset);
f1.out(result);
// rest of sc_main not shown
}
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49