anotation impedance circuit 1.8v pdf2 .pdf



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CR-1

:

@FALCON_LIB.FALCON(SCH_1):PAGE1

PAGE
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
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RULES:
1.)
2.)
3.)
4.)
5.)
6.)
7.)
8.)
9.)
10.)
12.)
13.)
14.)
15.)

CONTENTS

PAGE

COVER PAGE
CLOCK DIAGRAM
RESET/ENABLE
DIAGRAM
CPU, CLOCKS + EEPROM + STRAPPING
CPU, FSB
CPU, FSB POWER + PLL POWER
CPU, CORE POWER
CPU, POWER
CPU, DECOUPLING
CPU, DECOUPLING
CPU, DECOUPLING
GPU, FSB
GPU, VIDEO + PCIEX + EEPROM
GPU, MEMORY CONTROLLER A + B
GPU, MEMORY CONTROLLER C + D
GPU, PLL POWER + FSB POWER
GPU, CORE POWER + MEM POWER
GPU, DECOUPLING
MEMORY, A (TOP)
MEMORY, A MIRRORED (BOTTOM)
MEMORY, B (TOP)
MEMORY, B MIRRORED (BOTTOM)
MEMORY, C (TOP)
MEMORY, C MIRRORED (BOTTOM)
MEMORY, D (TOP)
MEMORY, D MIRRORED (BOTTOM)
HANA, CLOCKS + STRAPPING
HANA, VIDEO + FAN + JTAG
CONN, HDMI
HANA, POWER + DECOUPLING
HANA, POWER + DECOUPLING
POWER TRACE EMI CAPS

(APPLIED

[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
[43]
[44]
[45]
[46]
[47]
[48]
[49]
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[65-6]

SCHEMATIC
1.0

CONTENTS

REV

PCBA NUMBER
X8XXXXX-001

SB, PCIEX + SMM GPIO + JTAG
SB, SMC
SB, FLASH + USB + SPI
SB, ETHERNET + AUDIO + SATA
SB, STANDBY POWER + DECOUPLE
SB, MAIN POWER + DECOUPLE
SB OUT, ETHERNET
SB OUT, AUDIO
SB OUT, FLASH
SB OUT, FAN + INFRARED + BUTTONS
CONN, AVIP
CONN, RJ45 + USB COMBO
CONN, GAME PORTS + MEMORY PORTS
MISC, V_5P0 DUAL, DEBUG MAPPING
CONN, ODD AND HDD
CONN, ARGON + POWER
VREGS, INPUT + OUTPUT FILTERS
VREGS, CPU CONTROLLER
VREGS, GPU OUTPUT PHASE 1,2,3
VREGS, GPU CONTROLLER
VREGS, GPU OUTPUT PHASE 1,2
VREGS, SWITCHED 1.8,
5.0V
VREGS, LINEAR REGULATORS
XDK, DEBUG CONN
DEBUG BOARD, CPU + GPU BREAKOUT
DEBUG BOARD, CPU CONN
DEBUG BOARD, CPU CONN + TERM
DEBUG BOARD, CPU TERM
DEBUG BOARD, TITAN + YETI CONN
DEBUG BOARD, GPU CONN + TERM
XDK, LEDS, BDCM PHY
LABELS AND MOUNTING, PCI SWIZ
MEM QUAL BOARDS

PLEASE

BOM RELEASE

DATE

SIGNATURE

FALCON
RETAIL
REV 1.0
FAB D

FALCON_FABD
Tue

May 08

18:21:43

XX/XX/06

DATE

PB NUMBER

SPEC

X80XXXX-00X

DRN BY

MICROSOFT XBOX
TITLE

APVD

2007

REFER TO THE XENON DESIGN

CHK BY
ENGR
APVD

DRAWING

PAGE]

BOM RELEASE DATE
XX/XX/06

FALCON

WHEN POSSIBLE)

MSB TO LSB IS TOP TO BOTTOM
WHEN POSSIBLE:
INPUTS ON LEFT,
OUTPUTS ON RIGHT
ORDER OF PAGES=CHIP INTERFACES,
TERMINATION,
POWER, DECOUPLING
AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
LANED SIGNALS ARE GROUPED ON SYMBOLS
TRANSIMITTER
NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL
PAIRS
UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
SUFFIX _P FOR P JUNCTION
SUFFIX _EN FOR ENABLE
'CLK'
FOR CLOCKS, 'RST'
FOR RESETS
PWRGD FOR POWER GOOD

[PAGE_TITLE=COVER

REV
D

APVD

SCH,
MICROSOFT
CONFIDENTIAL

PBA,

FALCON

PROJECT NAME
FALCON_RETAIL

PAGE
1/82

REV
1.0

CR-2

:

@FALCON_LIB.FALCON(SCH_1):PAGE2

RJ45/USB
CONN

ENET
PHY

AVIP
CONN

*

FAN
CONN

I2S_MCLK(12.288MHZ)
I2S_BCLK(3.072MHZ)

AUDIO
DAC

OUT OF DATE *

POWER
CONN

ANA_XTAL_IN(27MHZ)

GPU VR

DEBUG
CONN
ANA
BCKUP

DVD
SATA
CONN

IS

CLOCK DIAGRAM

ENET_CLK(25MHZ)

SB

THIS

ANA
GPU VR
CNTL

STBY_CLK(48MHZ)
SATA_CLK_REF(25MHZ)
SATA_CLK_DP/DN(100MHZ)
PCIEX_CLK_DP/DN(100MHZ)
AUD_CLK(24.576MHZ)
CPU_CLK_DP/DN(100MHZ)
GPU_CLK_DP/DN

DVD
PWR
CONN
ANA
BCKUP

VR
FLSH

HDD
CONN

3P3

CPU

GPU
MA_CLK1_DP/DN(800MHZ)
MA_CLK0_DP/DN(800MHZ)
MB_CLK1_DP/DN(800MHZ)
MB_CLK0_DP/DN(800MHZ)

1P8

MEM
CLAM C+D

MC_CLK1_DP/DN(800MHZ)
MC_CLK0_DP/DN(800MHZ)
MD_CLK1_DP/DN(800MHZ)
MD_CLK0_DP/DN(800MHZ)

RISCWATCH
CONN

PIX_CLK_OUT_DP/DN(100MHZ)
(100MHZ)

TITAN
CONN

VR
VMEM VR
5P0

MPORT VR

MEM
CLAM A+B

EFUSE

CPU
VR

JTAG

VR

CPU VR
CNTL

VR

GAME
CONN
IR

EJECT
SW

<PAGE_TITLE=CLOCK

MEM
CONN

DIAGRAM>

MEM
CONN

BIND
SW

ARGON
CONN

DRAWING
FALCON_FABD
Tue May 08 11:47:32

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
2/82

REV
1.0

CR-3

:

@FALCON_LIB.FALCON(SCH_1):PAGE3

ENET
PHY

AVIP
CONN

ENET_RST_N

EXT_PWR_ON_N

RJ45/USB
CONN

POWER
CONN

FAN
CONN

RESET/ENABLE
AUD_CLAMP
AUD_RST_N

DIAGRAM

AUDIO
DAC

PSU_V12P0_EN

GPU VR
HANA_CLK_OE
HANA_RST_N

HANA

VREG_GPU_EN_N

SB_RST_N

SMC_RST_N
DVD
SATA
CONN

SB

VREG_GPU_PWRGD
EXT_PWR_ON_N
CPU_CHECKSTOP_N
CPU_RST_N
CPU_PWRGD
GPU_RST_N

RISCWATCH
CONN

MEM
CLAM C+D

MEM_RST
MEM_SCAN_EN
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN

3P3
VR

DEBUG
CONN

CPU
VR

GPU

CPU

MEM_RST
MEM_SCAN_EN
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN

HDD
CONN

VREG_CPU_PWRGD

SMC_DBG_EN

GPU_RST_DONE

VREG_3P3_EN

DVD
PWR
CONN

GPU VR
CNTL

VREG_1P8_EN_N
VREG_5P0_EN_N

CPU_PWRGD
TITAN
CONN

MEM
CLAM A+B
VMEM VR
5P0

EFUSE

JTAG

VR

CPU VR
CNTL

VR
VREG_EFUSE_EN

VREG_CPU_EN
GAME
CONN
IR

EJECT
SW

[PAGE_TITLE=RESET/ENABLE

MEM
CONN

MEM
CONN

DIAGRAM]

BIND
SW

ARGON
CONN

DRAWING
FALCON_FABD
Tue May 08 11:47:32

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
3/82

REV
1.0

CR-4

:

@FALCON_LIB.FALCON(SCH_1):PAGE4

58
34

FT2P11

3.92K
402

1

R7R10 2

3.92K
402

V_GPUCORE

2

1K
402

1

R6R6

10K
5%
CH
402

2

R7R11

1

6.19K
402

R6R4

2

R6R9

1%
CH

R6R5

1K
402

27

C7R112

27

1

2

1%
CH

IN

360PF
10%
50V
EMPTY
603

2

IN

2

2

10K
5%
CH
402

2

5%
CH

1
2

1

SMT

10K
5%
CH
402

1

R7D1

1

10K
5%
CH
402

2

10K
5%
EMPTY
402

C7

VREG_EFUSE_EN

FSB_CLK_DP
FSB_CLK_DN

FSB_HF_CLKOUT_DP
FSB_HF_CLKOUT_DN

AF20
AG20

CPU_FSB_HF_CLKOUT_DP
CPU_FSB_HF_CLKOUT_DN

OUT
OUT

CPU_FSB_CLK_SEL

AE16

FSB_CLK_SEL

AH23
AH22

CPU_EXT_CLK_EN

FSB_IMPED_CAL_DP
FSB_IMPED_CAL_DN

CPU_FSB_IMPED_CAL_DP
CPU_FSB_IMPED_CAL_DN

AD16

EXT_CLK_EN

OUT
OUT

CPU_PLL_BYPASS

AF14

PLL_BYPASS

AG14

PULSE_LIMIT_BYPASS

CPU_SYS_CONFIG0
CPU_SYS_CONFIG1

AH3
AE2

SYS_CONFIG0
SYS_CONFIG1

0
1
2
3
4

AF8
AG8
AH7
AH8
AH9

POST_IN0
POST_IN1
POST_IN2
POST_IN3
POST_IN4

CPU_SPI_SI

C4

V_CPUCORE

R7R8

2

100
5%
EMPTY
402

1

2

1

2

1

1

2

10K
5%
CH
402

1
10K
5%
EMPTY
402

2

10K
5%
CH
402

2

10K
5%
CH
402

1K
402

R7R1

AE22
AD22

ANL_1
ANL_2

CPU_SRVID
CPU_VGATE

A2
AH14

SRVID
VGATE

10K
5%
EMPTY
402

CPU_RES0_DP
CPU_RES0_DN

VDDS0_DP
VDDS0_DN

AF11
AH10

CPU_VDDS0_DP
CPU_VDDS0_DN

VDDS1_DP
VDDS1_DN

AG2
AH1

CPU_VDDS1_DP
CPU_VDDS1_DN

AE14

CPU_PSRO0_OUT

1
2

TP7R4

R7R2

2
2

1%
CH

10K
5%
CH
402

4

4

FTP
FTP
FTP
FTP
FTP

1
1
1
1
1

IN

TP

R7R9
CPU_SPI_CLK
CPU_SPI_EN
CPU_SPI_SO

OUT
OUT

4
4

TEMP_DP
TEMP_DN

AH18
AH19

CPU_TEMP_P
CPU_TEMP_N

IN
OUT

28
28

C5
B6
A5
B5
A6
C6

CPU_VREG_APS0
CPU_VREG_APS1
CPU_VREG_APS2
CPU_VREG_APS3
CPU_VREG_APS4
CPU_VREG_APS5

VID0
VID1
VID2
VID3
VID4
VID5

1
1
1

CPU

R7R1

R7R2

LOKI
ASPEN

1.40K
EMPTY

10K

OUT
OUT
OUT
OUT
OUT
OUT
1
1
1

FTP FT7T2
FTP FT7T1
FTP FT7T7

1K

IN

R6E2
1K
402

V_MEM

4
3
2
1
0

5%
CH

R7E7

CPU_SPI_SO
1K
402

DB7R1

1

B4
A3
A4

X806937-001

CPU_SPI_CLK

PROBE

1
2

SPI_CLK
SPI_EN
SPI_SO

5%
CH

6
5

CPU_SPI_CLK_R
CPU_SPI_SO_R

7
1
3

CPU_SPI_EN_R

SCK
SDI
HOLD_N*
CS_N*
WP_N*

VCC

8

SDO

2

2

R6E1

50
50
50
50
50
50

10K
5%
CH
402

1

1

.1UF
10%
6.3V
X5R
402

R7F3

10K
5%
EMPTY
402

2

2

CPU_SPI_SI_R
1

4

GND

C6F1

2

AT25020A

2

X800552-001

IN

CPU_SPI_EN

2

CLOCKS + EEPROM + STRAPPING]

10K
5%
CH
402

2

R7F2
1K
402

5%
CH

10K
402

1
2

5%
CH

10K
402

R7U3

4

R7E8

R7F1

1K
402

R7F7

1

CPU_SPI_SI

5%
CH

OUT

4

R7F4

V_MEM
2

1

10K
5%
CH
402

V_MEM
1

EMPTY

4

OUT

FTP FT7T5
FTP FT7T4
FTP FT7T3

V_MEM

U7E1

10K
5%
EMPTY
402

TP7R2
SMT

1

TE

R7R14

1%
CH

PROBE

1
2

SMT
PSRO0_OUT

1

R7R18

2

PROBE

AH12
AH13

RESISTOR0_DP
RESISTOR0_DN

V_MEM

FT7R4
FT7R6
FT7R2
FT7R1
FT7R5

[PAGE_TITLE=CPU,

AF2

SMT

56

OUT

TP7R3

SPI_SI

CPU_ANL_1
CPU_ANL_2

2

1

R7R19

2

EFU_POWERON

4

1
10K
5%
EMPTY
402

1

R7R23

3

R7R3

2

1

R7R22

2

R7R5

2

1

R7R13

1

R7R20

10K
5%
EMPTY
402

OUT
OUT

CPU_TEST_EN

1.40K
402

2

10K
5%
CH
402

OUT

1

0

IN

V_1P8

V_GPUCORE

2

4

R7T18

57

10K
5%
CH
402

PROBE

1
2

HARD_RESET_B
POWER_GOOD

1

100
5%
EMPTY
402

CPU_CORE_IF_BGR_PLL

SMT

MUST BE ACCESSIBLE

R7R12

TP7R1
AH15

AF1
AD14

V_GPUCORE

1

2

1

IC

CORE_IF_BGR_PLL

1

DB7R2

R7R15

10K
5%
CH
402

CORE_CLK_DP
CORE_CLK_DN

AH21
AH20

FSB_CLK_DP
FSB_CLK_DN

CPU_POST_IN<0..4>

R7R21

AG23
AF23

R7D2

V_GPUCORE

1

1 OF 10
LOKI

CPU_PULSE_LIMIT_BYPASS

2

LAYOUT:

U7D1

PROBE

5%
CH

R7R17

2

0
402

CPU_CLK_DP_C

TP6D1

1

R6R7

R6D5

CPU_CLK_DN1

2

5%
CH

CPU_CLK_DN_C

1

10K
5%
EMPTY
402

R6D4

0
402

360PF
10%
50V
EMPTY
603

1

R6R8

CLOCKS + EEPROM + STRAPPING

CPU_CLK_DP 1

C7R113

2

1

5%
CH

2

10K
5%
EMPTY
402

1

CPU_PWRGD_V1P1_N

1%
CH

V_GPUCORE

1

R7R16 2

1

1

FTP

CPU,

2

1%
CH

6.19K
402

CPU_PWRGD

IN

R7R4

1

1

FTP

FT2P12
34

CPU_RST_V1P1_N

OUT

CPU_RST_N

IN

100
5%
CH
402

1

5%
EMPTY

CPU_SPI_WP_N

IN

DRAWING
FALCON_FABD
Tue May 08 18:24:08

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
4/82

REV
1.0

CR-5

:

@FALCON_LIB.FALCON(SCH_1):PAGE5

CPU,

U7D1

FSB

2 OF 10

IC

LOKI
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

IN
IN

FSB_GP_CP0_FLAG_DP
FSB_GP_CP0_FLAG_DN

AB27
AB28

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

FSB_GP_CP0_DATA0_DP
FSB_GP_CP0_DATA0_DN
FSB_GP_CP0_DATA1_DP
FSB_GP_CP0_DATA1_DN
FSB_GP_CP0_DATA2_DP
FSB_GP_CP0_DATA2_DN
FSB_GP_CP0_DATA3_DP
FSB_GP_CP0_DATA3_DN
FSB_GP_CP0_DATA4_DP
FSB_GP_CP0_DATA4_DN
FSB_GP_CP0_DATA5_DP
FSB_GP_CP0_DATA5_DN
FSB_GP_CP0_DATA6_DP
FSB_GP_CP0_DATA6_DN
FSB_GP_CP0_DATA7_DP
FSB_GP_CP0_DATA7_DN

T26
T25
T28
T27
U27
U28
V26
V25
W27
W28
Y26
Y25
Y28
Y27
AA27
AA28

IN
IN

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

IN
IN

FSB_GP_CP0_CLK_DP
FSB_GP_CP0_CLK_DN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

V28
V27

CP_GP0_CLK_DP
CP_GP0_CLK_DN

AE27
AE28

FSB_CP_GP0_CLK_DP
FSB_CP_GP0_CLK_DN

OUT
OUT

12
12

CP_GP0_FLAG_DP
CP_GP0_FLAG_DN

AH25
AH26

FSB_CP_GP0_FLAG_DP
FSB_CP_GP0_FLAG_DN

OUT
OUT

12
12

CP_GP0_DATA0_DP
CP_GP0_DATA0_DN
CP_GP0_DATA1_DP
CP_GP0_DATA1_DN
CP_GP0_DATA2_DP
CP_GP0_DATA2_DN
CP_GP0_DATA3_DP
CP_GP0_DATA3_DN
CP_GP0_DATA4_DP
CP_GP0_DATA4_DN
CP_GP0_DATA5_DP
CP_GP0_DATA5_DN
CP_GP0_DATA6_DP
CP_GP0_DATA6_DN
CP_GP0_DATA7_DP
CP_GP0_DATA7_DN

AB26
AB25
AC27
AC28
AD28
AD27
AD25
AD26
AF28
AF27
AF25
AF26
AG27
AG28
AH28
AH27

FSB_CP_GP0_DATA0_DP
FSB_CP_GP0_DATA0_DN
FSB_CP_GP0_DATA1_DP
FSB_CP_GP0_DATA1_DN
FSB_CP_GP0_DATA2_DP
FSB_CP_GP0_DATA2_DN
FSB_CP_GP0_DATA3_DP
FSB_CP_GP0_DATA3_DN
FSB_CP_GP0_DATA4_DP
FSB_CP_GP0_DATA4_DN
FSB_CP_GP0_DATA5_DP
FSB_CP_GP0_DATA5_DN
FSB_CP_GP0_DATA6_DP
FSB_CP_GP0_DATA6_DN
FSB_CP_GP0_DATA7_DP
FSB_CP_GP0_DATA7_DN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CP_GP1_CLK_DP
CP_GP1_CLK_DN

M28
M27

FSB_CP_GP1_CLK_DP
FSB_CP_GP1_CLK_DN

OUT
OUT

12
12

CP_GP1_FLAG_DP
CP_GP1_FLAG_DN

R28
R27

FSB_CP_GP1_FLAG_DP
FSB_CP_GP1_FLAG_DN

OUT
OUT

12
12

CP_GP1_DATA0_DP
CP_GP1_DATA0_DN
CP_GP1_DATA1_DP
CP_GP1_DATA1_DN
CP_GP1_DATA2_DP
CP_GP1_DATA2_DN
CP_GP1_DATA3_DP
CP_GP1_DATA3_DN
CP_GP1_DATA4_DP
CP_GP1_DATA4_DN
CP_GP1_DATA5_DP
CP_GP1_DATA5_DN
CP_GP1_DATA6_DP
CP_GP1_DATA6_DN
CP_GP1_DATA7_DP
CP_GP1_DATA7_DN

J28
J27
K28
K27
L25
L26
L28
L27
N25
N26
N28
N27
P28
P27
R25
R26

FSB_CP_GP1_DATA0_DP
FSB_CP_GP1_DATA0_DN
FSB_CP_GP1_DATA1_DP
FSB_CP_GP1_DATA1_DN
FSB_CP_GP1_DATA2_DP
FSB_CP_GP1_DATA2_DN
FSB_CP_GP1_DATA3_DP
FSB_CP_GP1_DATA3_DN
FSB_CP_GP1_DATA4_DP
FSB_CP_GP1_DATA4_DN
FSB_CP_GP1_DATA5_DP
FSB_CP_GP1_DATA5_DN
FSB_CP_GP1_DATA6_DP
FSB_CP_GP1_DATA6_DN
FSB_CP_GP1_DATA7_DP
FSB_CP_GP1_DATA7_DN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

GP_CP0_CLK_DP
GP_CP0_CLK_DN
GP_CP0_FLAG_DP
GP_CP0_FLAG_DN
GP_CP0_DATA0_DP
GP_CP0_DATA0_DN
GP_CP0_DATA1_DP
GP_CP0_DATA1_DN
GP_CP0_DATA2_DP
GP_CP0_DATA2_DN
GP_CP0_DATA3_DP
GP_CP0_DATA3_DN
GP_CP0_DATA4_DP
GP_CP0_DATA4_DN
GP_CP0_DATA5_DP
GP_CP0_DATA5_DN
GP_CP0_DATA6_DP
GP_CP0_DATA6_DN
GP_CP0_DATA7_DP
GP_CP0_DATA7_DN

FSB_GP_CP1_CLK_DP
FSB_GP_CP1_CLK_DN

E28
E27

FSB_GP_CP1_FLAG_DP
FSB_GP_CP1_FLAG_DN

J26
J25

GP_CP1_FLAG_DP
GP_CP1_FLAG_DN

FSB_GP_CP1_DATA0_DP
FSB_GP_CP1_DATA0_DN
FSB_GP_CP1_DATA1_DP
FSB_GP_CP1_DATA1_DN
FSB_GP_CP1_DATA2_DP
FSB_GP_CP1_DATA2_DN
FSB_GP_CP1_DATA3_DP
FSB_GP_CP1_DATA3_DN
FSB_GP_CP1_DATA4_DP
FSB_GP_CP1_DATA4_DN
FSB_GP_CP1_DATA5_DP
FSB_GP_CP1_DATA5_DN
FSB_GP_CP1_DATA6_DP
FSB_GP_CP1_DATA6_DN
FSB_GP_CP1_DATA7_DP
FSB_GP_CP1_DATA7_DN

C26
C25
C28
C27
D27
D28
E26
E25
F27
F28
G26
G25
G28
G27
H27
H28

GP_CP1_DATA0_DP
GP_CP1_DATA0_DN
GP_CP1_DATA1_DP
GP_CP1_DATA1_DN
GP_CP1_DATA2_DP
GP_CP1_DATA2_DN
GP_CP1_DATA3_DP
GP_CP1_DATA3_DN
GP_CP1_DATA4_DP
GP_CP1_DATA4_DN
GP_CP1_DATA5_DP
GP_CP1_DATA5_DN
GP_CP1_DATA6_DP
GP_CP1_DATA6_DN
GP_CP1_DATA7_DP
GP_CP1_DATA7_DN

GP_CP1_CLK_DP
GP_CP1_CLK_DN

X806937-001

V_GPUCORE

1
2

[PAGE_TITLE=CPU,

FSB]

C6R15
.1UF
10%
6.3V
X5R
402

1
2

C6R18

.1UF
10%
6.3V
X5R
402

1
2

C6R14

.1UF
10%
6.3V
X5R
402

1
2

C6R25
.1UF
10%
6.3V
X5R
402

1
2

C6R37

.1UF
10%
6.3V
X5R
402

1
2

C6T19
.1UF
10%
6.3V
X5R
402

1
2

C6T7
.1UF
10%
6.3V
X5R
402

1
2

C6T27

.1UF
10%
6.3V
X5R
402

1
2

C6T33

.1UF
10%
6.3V
X5R
402

1
2

C6T32

.1UF
10%
6.3V
X5R
402

1
2

C6R6
.1UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:09

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
5/82

REV
1.0

CR-6

:

@FALCON_LIB.FALCON(SCH_1):PAGE6

CPU,

FSB POWER + PLL

POWER

V_1P8
V_GPUCORE

V_CPUPLL

U7D1

FB7R1
1

1
2

C7R1

1
2

FB
603

1K
0.2A
0.7DCR

2

1

.1UF
10%
6.3V
X5R
402

C7R7

.1UF
10%
6.3V
X5R
402

2

C7R116
.1UF
10%
6.3V
X5R
402

1

4 of

C7R114

.1UF
10%
6.3V
X5R
402

2

ST7R1
2

V_EFUSE

SHORT

2

FB6D1
1

1
2

C6D1

10K
402

2

1K
0.2A
0.7DCR

R7T2

1

CPU_VDDE

5%
CH

FB
603

1

.1UF
10%
6.3V
X5R
402

2.2UF
10%
6.3V
X5R
603

2

V_CPU_CORE_HF_VDDA_PLL
V_CPU_CORE_HF_GNDA_PLL

ST6D1
2

1

V_CPU_CORE_IF_VDDA_PLL
V_CPU_CORE_IF_GNDA_PLL

SHORT

V_CPU_FSB_HF_VDDA_PLL
V_CPU_FSB_HF_GNDA_PLL

FB6R1
1

1
2

C6R2

V_CPU_FSB_IF_VDDA_PLL

2

1K
0.2A
0.7DCR

V_CPU_FSB_IF_GNDA_PLL

FB
603

V_CPU_VDDA_RNG

1

.1UF
10%
6.3V
X5R
402

V_CPU_GNDA_RNG

C6R4

VDD_IO
VDDE
VDDE_SEC

AG17
AF17

CORE_HF_VDDA_PLL
CORE_HF_GNDA_PLL

AH17
AH16

CORE_IF_VDDA_PLL
CORE_IF_GNDA_PLL

AD20
AE20

FSB_HF_VDDA_PLL
FSB_HF_GNDA_PLL

AD18
AE18

FSB_IF_VDDA_PLL
FSB_IF_GNDA_PLL

AH11
AG11

VDDA_RNG
GNDA_RNG

2.2UF
10%
6.3V
X5R
603

2
ST6R1
2

1

AH4
A7
B7

C6D4

10

IC

LOKI

2.2UF
10%
6.3V
X5R
603

2
1

C7R115

1

VDD_FSB0
VDD_FSB1
VDD_FSB2
VDD_FSB3
VDD_FSB4
VDD_FSB5
VDD_FSB6
VDD_FSB7
VDD_FSB8
VDD_FSB9
VDD_FSB10
VDD_FSB11
VDD_FSB12
VDD_FSB13
VDD_FSB14
VDD_FSB15
VDD_FSB16
VDD_FSB17
VDD_FSB18
VDD_FSB19
VDD_FSB20
VDD_FSB21
VDD_FSB22
VDD_FSB23
VDD_FSB24
VDD_FSB25
VDD_FSB26
VDD_FSB27
VDD_FSB28
VDD_FSB29
VDD_FSB30
VDD_FSB31
VDD_FSB32
VDD_FSB33
VDD_FSB34

AA25
AB24
AC25
AD24
AE25
AF24
AG25
AH24
B11
B15
B19
B23
B27
C24
D8
D12
D16
D20
D25
E24
F25
G24
H25
J24
K25
L24
M25
N24
P25
R24
T24
U25
V24
W25
Y24

SHORT

FB6R2
1

1
2

C6R3

2

1K
0.2A
0.7DCR

FB
603

1

.1UF
10%
6.3V
X5R
402

2
1

ST6R2
2

C6R5
2.2UF
10%
6.3V
X5R
603

X806937-001

SHORT

FB7D1
1

C7D1

2

1K
0.2A
0.7DCR

FB
603

1

1UF
10%
16V
EMPTY
603

2
1

ST7D1
2

C7D2
2.2UF
10%
6.3V
X5R
603

SHORT

[PAGE_TITLE=CPU,

FSB POWER + PLL

POWER]

DRAWING
FALCON_FABD
Tue May 08 18:24:09

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
6/82

REV
1.0

CR-7

:

@FALCON_LIB.FALCON(SCH_1):PAGE7

CPU,
V_CPUCORE

V_CPUCORE

IC

U7D1
5 of

V_CPUCORE

U7D1

10

6 of

LOKI
AA2
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AB1
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC2
AC4
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AD1
AD3
AD5
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AE1
AE4

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47

CORE POWER

10

V_CPUCORE

IC

V_CPUCORE

U7D1

AE6
AE8
AE10
AE12
AF4
AF7
AF10
AF13
AG3
AG6
AG9
AG12
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
H1
H3
H5
H7
H9
H11
H13
H15
H17
H19
H21
H23
J2
J4
J6
J8
J10
J12
J14
J16
J18
J20
J22
K1
K3

K5
K7
K9
K11
K13
K15
K17
K19
K21
K23
L2
L4
L6
L8
L10
L12
L14
L16
L18
L20
L22
M1
M3
M5
M7
M9
M11
M13
M15
M17
M19
M21
M23
N2
N4
N6
N8
N10
N12
N14
N16
N18
N20
N22
P1
P3
P5

VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD134
VDD135
VDD136
VDD137
VDD138
VDD139
VDD140
VDD141
VDD142
X806937-001

10

LOKI

LOKI
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
VDD93
VDD94
VDD95

V_CPUVCS

IC
7 of

VDD143
VDD144
VDD145
VDD146
VDD147
VDD148
VDD149
VDD150
VDD151
VDD152
VDD153
VDD154
VDD155
VDD156
VDD157
VDD158
VDD159
VDD160
VDD161
VDD162
VDD163
VDD164
VDD165
VDD166
VDD167
VDD168
VDD169
VDD170
VDD171
VDD172
VDD173
VDD174
VDD175
VDD176
VDD177
VDD178
VDD179
VDD180
VDD181
VDD182
VDD183
VDD184
VDD185
VDD186
VDD187
VDD188
VDD189

P7
P9
P11
P13
P15
P17
P19
P21
P23
R2
R4
R6
R8
R10
R12
R14
R16
R18
R20
R22
T1
T3
T5
T7
T9
T11
T13
T15
T17
T19
T21
T23
U2
U4
U6
U8
U10
U12
U14
U16
U18
U20
U22
V1
V3
V5
V7

V9
V11
V13
V15
V17
V19
V21
V23
W2
W4
W6
W8
W10
W12
W14
W16
W18
W20
W22
Y1
Y3
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23

VDD190
VDD191
VDD192
VDD193
VDD194
VDD195
VDD196
VDD197
VDD198
VDD199
VDD200
VDD201
VDD202
VDD203
VDD204
VDD205
VDD206
VDD207
VDD208
VDD209
VDD210
VDD211
VDD212
VDD213
VDD214
VDD215
VDD216
VDD217
VDD218
VDD219
VDD220

VCS0
VCS1
VCS2
VCS3
VCS4
VCS5
VCS6
VCS7
VCS8
VCS9
VCS10
VCS11
VCS12
VCS13
VCS14
VCS15

B1
B3
C1
C2
C3
D1
D3
D4
D5
E2
E4
E6
F1
F3
F5
F7

X806937-001

X806937-001

[PAGE_TITLE=CPU,

CORE POWER]

DRAWING
FALCON_FABD
Tue May 08 18:24:10

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
7/82

REV
1.0

CR-8

:

@FALCON_LIB.FALCON(SCH_1):PAGE8

CPU,

U7D1

9 of

10

U7D1

10

IC
10

LOKI

LOKI
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

IC

U7D1

IC
8 of

AA1
AA3
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA24
AA26
AB2
AB4
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC1
AC3
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC26
AD2
AD4
AD6
AD8
AD10
AD12
AE3
AE5
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE24
AE26

POWER

VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116

AF3
AF6
AF9
AF12
AF15
AF16
AF18
AF19
AF21
AF22
AG4
AG7
AG10
AG13
AG15
AG16
AG18
AG19
AG21
AG22
AG24
AG26
B2
B9
B13
B17
B21
B25
B28
D2
D6
D10
D14
D18
D22
D24
D26
E1
E3
E5
E7
E9
E11
E13
E15
E17
E19
E21
E23
F2
F4
F6
F8
F10
F12
F14
F16
F18
F20

F22
F24
F26
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
H2
H4
H6
H8
H10
H12
H14
H16
H18
H20
H22
H24
H26
J1
J3
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K4
K6
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
L1
L3
L5
L7
L9

VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
X806937-001

of

10

LOKI
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232

L11
L13
L15
L17
L19
L21
L23
M2
M4
M6
M8
M10
M12
M14
M16
M18
M20
M22
M24
M26
N1
N3
N5
N7
N9
N11
N13
N15
N17
N19
N21
N23
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
R1
R3
R5
R7
R9
R11
R13
R15
R17
R19
R21
R23
T2

T4
T6
T8
T10
T12
T14
T16
T18
T20
T22
U1
U3
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
U24
U26
V2
V4
V6
V8
V10
V12
V14
V16
V18
V20
V22
W1
W3
W5
W7
W9
W11
W13
W15
W17
W19
W21
W23
W24
W26
Y2
Y4
Y6
Y8
Y10
Y12
Y14
Y16
Y18

VSS291
VSS292

VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290

Y20
Y22

X806937-001

X806937-001

[PAGE_TITLE=CPU,

POWER]

DRAWING
FALCON_FABD
Tue May 08 18:24:10

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
8/82

REV
1.0

CR-9

:

@FALCON_LIB.FALCON(SCH_1):PAGE9

CPU,

V_CPUCORE

1

C7T94

2

4.7UF 10%
6.3V
EMPTY
805

1

C7T93

2

4.7UF 10%
6.3V
EMPTY
805

1

C7T33

2

4.7UF 10%
6.3V
X5R
805

C7R2

1

2

4.7UF 10%
6.3V
X5R
805

1

C7E10

C7T32

2

4.7UF 10%
6.3V
X5R
805

1

C7R26

2

4.7UF 10%
6.3V
X5R
805

1

C7E9

2

4.7UF 10%
6.3V
EMPTY
805

1

C7T1

2

4.7UF 10%
6.3V
X5R
805

1

C7T6

2

4.7UF 10%
6.3V
X5R
805

[PAGE_TITLE=CPU,

DECOUPLING]

C7E6

2

1

C7D12

2

4.7UF 10%
6.3V
X5R
805

1

C7D19

1

C7D3

2

4.7UF 10%
6.3V
X5R
805

1

2

4.7UF 10%
6.3V
EMPTY
805

1

C7E5

2

4.7UF 10%
6.3V
X5R
805

1

C7D5

2

4.7UF 10%
6.3V
EMPTY
805

C7R121

1

2

4.7UF 10%
6.3V
EMPTY
805

1

C7R23

2

4.7UF 10%
6.3V
X5R
805

1

C7R24

1

C7R3

2

4.7UF 10%
6.3V
X5R
805

2

4.7UF 10%
6.3V
X5R
805

1

C7E1

2

4.7UF 10%
6.3V
X5R
805
C7R119

2

4.7UF 10%
6.3V
EMPTY
805

C7R120

2

4.7UF 10%
6.3V
EMPTY
805

1

1

4.7UF 10%
6.3V
X5R
805

DECOUPLING

1

2

4.7UF 10%
6.3V
EMPTY
805

1

C7R90

2

4.7UF 10%
6.3V
X5R
805

1

C7E2

2

4.7UF 10%
6.3V
X5R
805

1

C7T83

2

4.7UF 10%
6.3V
X5R
805

1

C7D11

2

4.7UF 10%
6.3V
X5R
805

1

C7T84

2

4.7UF 10%
6.3V
X5R
805

1

C6T1

2

4.7UF 10%
6.3V
X5R
805

1

C7R30

2

4.7UF 10%
6.3V
X5R
805

1

C7R27

2

4.7UF 10%
6.3V
X5R
805

1

C7D8

2

4.7UF 10%
6.3V
X5R
805

1

C7D4

2

4.7UF 10%
6.3V
X5R
805

1

C7D18

2

4.7UF 10%
6.3V
EMPTY
805

1

C7D7

2

4.7UF 10%
6.3V
X5R
805

1

C7R91

1

C6R7

2

4.7UF 10%
6.3V
X5R
805

1

C6R10

2

4.7UF 10%
6.3V
X5R
805

1

C7R28

2

4.7UF 10%
6.3V
X5R
805

1

C7R29

2

4.7UF 10%
6.3V
X5R
805

1

C7T4

2

4.7UF 10%
6.3V
X5R
805

2

4.7UF 10%
6.3V
X5R
805

1

C7T5

2

4.7UF 10%
6.3V
X5R
805

1

C7R5

2

4.7UF 10%
6.3V
X5R
805

1

C7R4

2

4.7UF 10%
6.3V
X5R
805

1

C7R25

2

4.7UF 10%
6.3V
X5R
805

DRAWING
FALCON_FABD
Tue May 08 18:24:11

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
9/82

REV
1.0

CR-10

:

@FALCON_LIB.FALCON(SCH_1):PAGE10

CPU,

V_CPUCORE

1

C7R49

2

.1UF 10%
6.3V
X5R
402

1

C7R44

2

.1UF 10%
6.3V
X5R
402

1

C6R29

2

.1UF 10%
6.3V
X5R
402

1

C6R28

2

.1UF 10%
6.3V
X5R
402

1

C6R17

2

.1UF 10%
6.3V
X5R
402

1

C7R76

2

.1UF 10%
6.3V
X5R
402

1

C6R39

2

.1UF 10%
6.3V
X5R
402

1

C6R42

2

.1UF 10%
6.3V
X5R
402

1

C7R67

2

.1UF 10%
6.3V
X5R
402

1

C7T3

2

.1UF 10%
6.3V
X5R
402

[PAGE_TITLE=CPU,

DECOUPLING]

1

C7T9

2

.1UF 10%
6.3V
X5R
402

1

C7R22

2

.1UF 10%
6.3V
X5R
402

1

C7R35

2

.1UF 10%
6.3V
X5R
402

1

C7R34

2

.1UF 10%
6.3V
X5R
402

1

C7R19

2

.1UF 10%
6.3V
X5R
402

1

C7R43

2

.1UF 10%
6.3V
X5R
402

1

C6R16

2

.1UF 10%
6.3V
X5R
402

1

C6R19

2

.1UF 10%
6.3V
X5R
402

1

C7R61

2

.1UF 10%
6.3V
X5R
402

1

C6R35

2

.1UF 10%
6.3V
X5R
402

1

C6R44

2

.1UF 10%
6.3V
X5R
402

1

C6R32

2

.1UF 10%
6.3V
X5R
402

C7R102

1

2

.1UF 10%
6.3V
X5R
402

1

C7R81

2

.1UF 10%
6.3V
X5R
402

1

C7R68

2

.1UF 10%
6.3V
X5R
402

1

C7R69

2

.1UF 10%
6.3V
X5R
402

1

C7R57

2

.1UF 10%
6.3V
X5R
402

1

C6R20

2

.1UF 10%
6.3V
X5R
402

1

C6R21

2

.1UF 10%
6.3V
X5R
402

1

C6T26

2

.1UF 10%
6.3V
X5R
402

DECOUPLING

1

C7R52

2

.1UF 10%
6.3V
X5R
402

1

C7R51

2

.1UF 10%
6.3V
X5R
402

1

C7R50

2

.1UF 10%
6.3V
X5R
402

1

C6T6

2

.1UF 10%
6.3V
X5R
402

1

C6R36

2

.1UF 10%
6.3V
X5R
402

1

C6R23

2

.1UF 10%
6.3V
X5R
402

1

C7R58

2

.1UF 10%
6.3V
X5R
402

1

C7R59

2

.1UF 10%
6.3V
X5R
402

1

C7R60

2

.1UF 10%
6.3V
X5R
402

1

C7T2

2

.1UF 10%
6.3V
X5R
402

1

C6T10

2

.1UF 10%
6.3V
X5R
402

1

C7T22

2

.1UF 10%
6.3V
X5R
402

1

C7T27

2

.1UF 10%
6.3V
X5R
402

1

C7R48

2

.1UF 10%
6.3V
X5R
402

1

C7T51

1

C7T21

2

.1UF 10%
6.3V
X5R
402

1

C6T2

2

.1UF 10%
6.3V
X5R
402

1

C7T10

2

.1UF 10%
6.3V
X5R
402

C7R111

1

2

.1UF 10%
6.3V
X5R
402

2

.1UF 10%
6.3V
X5R
402

1

C7T37

2

.1UF 10%
6.3V
X5R
402

1

C7R89

2

.1UF 10%
6.3V
X5R
402

1

C6T25

2

.1UF 10%
6.3V
X5R
402

1

C7R99

2

.1UF 10%
6.3V
X5R
402

C7R100

1

2

.1UF 10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:11

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
10/82

REV
1.0

CR-11

:

@FALCON_LIB.FALCON(SCH_1):PAGE11

CPU,

DECOUPLING

V_CPUCORE

V_CPUVCS

N:EMPTIES
1

C7R31

2

.1UF 10%
6.3V
X5R
402

1

C7T54

2

.1UF 10%
6.3V
X5R
402

1

C6T16

2

.1UF 10%
6.3V
X5R
402

1

C7R56

2

.1UF 10%
6.3V
X5R
402

1

C6R26

2

.1UF 10%
6.3V
X5R
402

1

C6T9

2

.1UF 10%
6.3V
X5R
402

1

C6T3

2

.1UF 10%
6.3V
X5R
402

1

C7R21

2

.1UF 10%
6.3V
X5R
402

1

C6R41

2

.1UF 10%
6.3V
X5R
402

1

C6R13

2

.1UF 10%
6.3V
X5R
402

[PAGE_TITLE=CPU,

1

C7T25

2

.1UF 10%
6.3V
X5R
402

1

C6T24

2

.1UF 10%
6.3V
X5R
402

1

C6T13

2

.1UF 10%
6.3V
X5R
402

1

C7R20

2

.1UF 10%
6.3V
X5R
402

1

C7R42

2

.1UF 10%
6.3V
X5R
402

1

C7R41

2

.1UF 10%
6.3V
X5R
402

1

C7R40

2

.1UF 10%
6.3V
X5R
402

1

C7R39

2

.1UF 10%
6.3V
X5R
402

1

C6T21

2

.1UF 10%
6.3V
X5R
402

1

C6R12

2

.1UF 10%
6.3V
X5R
402

DECOUPLING]

1

C7T38

2

.1UF 10%
6.3V
X5R
402

C7R110

1

2

.1UF 10%
6.3V
X5R
402

1

C6T14

2

.1UF 10%
6.3V
X5R
402

1

C7T28

2

.1UF 10%
6.3V
X5R
402

1

C7R14

2

.1UF 10%
6.3V
X5R
402

1

C7T49

2

.1UF 10%
6.3V
X5R
402

1

C6T22

2

.1UF 10%
6.3V
X5R
402

1

C7T41

2

.1UF 10%
6.3V
X5R
402

1

C7R33

2

.1UF 10%
6.3V
X5R
402

1

C7R32

2

.1UF 10%
6.3V
X5R
402

1

C7T58

2

.1UF 10%
6.3V
X5R
402

1

C6R24

2

.1UF 10%
6.3V
X5R
402

1

C7T56

2

.1UF 10%
6.3V
X5R
402

1

C7T50

2

.1UF 10%
6.3V
X5R
402

C7R106

1

2

.1UF 10%
6.3V
X5R
402

1

C7T11

2

.1UF 10%
6.3V
X5R
402

1

C7T40

2

.1UF 10%
6.3V
X5R
402

1

C7R75

2

.1UF 10%
6.3V
X5R
402

1

C7T47

2

.1UF 10%
6.3V
X5R
402

1

C7T46

2

.1UF 10%
6.3V
X5R
402

1

C6T17

2

.1UF 10%
6.3V
X5R
402

1

C7R95

2

.1UF 10%
6.3V
X5R
402

1

C6T18

2

.1UF 10%
6.3V
X5R
402

C7R101

1

2

.1UF 10%
6.3V
X5R
402

1

C7T57

2

.1UF 10%
6.3V
X5R
402

1

C7T55

2

.1UF 10%
6.3V
X5R
402

1

C7R83

2

.1UF 10%
6.3V
X5R
402

1

C7T39

2

.1UF 10%
6.3V
X5R
402

1

C7T26

2

.1UF 10%
6.3V
X5R
402

1

C7T48

2

.1UF 10%
6.3V
X5R
402

1

C7R66

2

.1UF 10%
6.3V
EMPTY
402

1

C6T4

2

.1UF 10%
6.3V
EMPTY
402

1

C7T15

2

.1UF 10%
6.3V
EMPTY
402

1

C7T24

2

.1UF 10%
6.3V
EMPTY
402

1

C6T11

2

.1UF 10%
6.3V
EMPTY
402

1

C7R74

2

.1UF 10%
6.3V
EMPTY
402

1

C6R30

2

.1UF 10%
6.3V
EMPTY
402

1

C7R82

2

.1UF 10%
6.3V
EMPTY
402

1

C7T23

2

.1UF 10%
6.3V
EMPTY
402

1

C7R65

2

.1UF 10%
6.3V
EMPTY
402

DRAWING
FALCON_FABD
Tue May 08 18:24:12

1

C7T7

2

.1UF 10%
6.3V
X5R
402

1

C7T14

2

.1UF 10%
6.3V
X5R
402

1

C7T12

2

.1UF 10%
6.3V
X5R
402

1

C7T13

1

C7T29

2

.1UF 10%
6.3V
X5R
402

1

C7T30

2

.1UF 10%
6.3V
X5R
402

1

C7T31

2

.1UF 10%
6.3V
X5R
402

2

.1UF 10%
6.3V
X5R
402

1

C7T8

2

.1UF 10%
6.3V
X5R
402

1

C7T16

2

.1UF 10%
6.3V
X5R
402

1

C7T17

2

.1UF 10%
6.3V
X5R
402

1

C7T18

2

.1UF 10%
6.3V
X5R
402

1

C7T19

2

.1UF 10%
6.3V
X5R
402

1

C7T20

2

.1UF 10%
6.3V
X5R
402

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
11/82

REV
1.0

CR-12

:

@FALCON_LIB.FALCON(SCH_1):PAGE12

V_MEM

GPU,

V_GPUCORE

R5C12 1

2
1K
402

1

R5R1

2

1K
402

1

2

1K
5%
CH
402

1
49.9
402

R4R9

GPU Y2

5%
CH

FSB_BYPCLK_DP
FSB_BYPCLK_DN
FSB_BYPCLK_SEL

B29
A29
D25
J34
J33
J30
J29

CP_GP0_CLK_DP
CP_GP0_CLK_DN
CP_GP0_FLAG_DP
CP_GP0_FLAG_DN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

FSB_CP_GP0_DATA0_DP
FSB_CP_GP0_DATA0_DN
FSB_CP_GP0_DATA1_DP
FSB_CP_GP0_DATA1_DN
FSB_CP_GP0_DATA2_DP
FSB_CP_GP0_DATA2_DN
FSB_CP_GP0_DATA3_DP
FSB_CP_GP0_DATA3_DN
FSB_CP_GP0_DATA4_DP
FSB_CP_GP0_DATA4_DN
FSB_CP_GP0_DATA5_DP
FSB_CP_GP0_DATA5_DN
FSB_CP_GP0_DATA6_DP
FSB_CP_GP0_DATA6_DN
FSB_CP_GP0_DATA7_DP
FSB_CP_GP0_DATA7_DN

M29
M30
L32
L31
K33
K34
L30
L29
J31
J32
K30
K29
H34
H33
H31
H32

CP_GP0_DATA0_DP
CP_GP0_DATA0_DN
CP_GP0_DATA1_DP
CP_GP0_DATA1_DN
CP_GP0_DATA2_DP
CP_GP0_DATA2_DN
CP_GP0_DATA3_DP
CP_GP0_DATA3_DN
CP_GP0_DATA4_DP
CP_GP0_DATA4_DN
CP_GP0_DATA5_DP
CP_GP0_DATA5_DN
CP_GP0_DATA6_DP
CP_GP0_DATA6_DN
CP_GP0_DATA7_DP
CP_GP0_DATA7_DN

5
5
5
5

IN
IN
IN
IN

FSB_CP_GP1_CLK_DP
FSB_CP_GP1_CLK_DN
FSB_CP_GP1_FLAG_DP
FSB_CP_GP1_FLAG_DN

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

FSB_CP_GP1_DATA0_DP
FSB_CP_GP1_DATA0_DN
FSB_CP_GP1_DATA1_DP
FSB_CP_GP1_DATA1_DN
FSB_CP_GP1_DATA2_DP
FSB_CP_GP1_DATA2_DN
FSB_CP_GP1_DATA3_DP
FSB_CP_GP1_DATA3_DN
FSB_CP_GP1_DATA4_DP
FSB_CP_GP1_DATA4_DN
FSB_CP_GP1_DATA5_DP
FSB_CP_GP1_DATA5_DN
FSB_CP_GP1_DATA6_DP
FSB_CP_GP1_DATA6_DN
FSB_CP_GP1_DATA7_DP
FSB_CP_GP1_DATA7_DN

2

1%
EMPTY

GPU

R5R3

R4R9

B13L
GUNGA

STUFF
EMPTY

EMPTY
STUFF

V33
V34
T33
T34

FSB_IMPED_CAL
FSB_IMPED_NCAL

1

R5R3

2

4.87K
1%
CH
402

1
2

VERSION

1

1

13

GP_CP0_CLK_DP
GP_CP0_CLK_DN
GP_CP0_FLAG_DP
GP_CP0_FLAG_DN

P33
P34
L34
L33

FSB_GP_CP0_CLK_DP
FSB_GP_CP0_CLK_DN
FSB_GP_CP0_FLAG_DP
FSB_GP_CP0_FLAG_DN

GP_CP0_DATA0_DP
GP_CP0_DATA0_DN
GP_CP0_DATA1_DP
GP_CP0_DATA1_DN
GP_CP0_DATA2_DP
GP_CP0_DATA2_DN
GP_CP0_DATA3_DP
GP_CP0_DATA3_DN
GP_CP0_DATA4_DP
GP_CP0_DATA4_DN
GP_CP0_DATA5_DP
GP_CP0_DATA5_DN
GP_CP0_DATA6_DP
GP_CP0_DATA6_DN
GP_CP0_DATA7_DP
GP_CP0_DATA7_DN

T29
T30
T31
T32
R34
R33
R29
R30
N34
N33
P29
P30
N31
N32
M34
M33

FSB_GP_CP0_DATA0_DP
FSB_GP_CP0_DATA0_DN
FSB_GP_CP0_DATA1_DP
FSB_GP_CP0_DATA1_DN
FSB_GP_CP0_DATA2_DP
FSB_GP_CP0_DATA2_DN
FSB_GP_CP0_DATA3_DP
FSB_GP_CP0_DATA3_DN
FSB_GP_CP0_DATA4_DP
FSB_GP_CP0_DATA4_DN
FSB_GP_CP0_DATA5_DP
FSB_GP_CP0_DATA5_DN
FSB_GP_CP0_DATA6_DP
FSB_GP_CP0_DATA6_DN
FSB_GP_CP0_DATA7_DP
FSB_GP_CP0_DATA7_DN

AA31
AA32
Y33
Y34
W30
W29
W33
W34
V29
V28
V31
V32
U33
U34
U30
U29

CP_GP1_DATA0_DP
CP_GP1_DATA0_DN
CP_GP1_DATA1_DP
CP_GP1_DATA1_DN
CP_GP1_DATA2_DP
CP_GP1_DATA2_DN
CP_GP1_DATA3_DP
CP_GP1_DATA3_DN
CP_GP1_DATA4_DP
CP_GP1_DATA4_DN
CP_GP1_DATA5_DP
CP_GP1_DATA5_DN
CP_GP1_DATA6_DP
CP_GP1_DATA6_DN
CP_GP1_DATA7_DP
CP_GP1_DATA7_DN

T28
AA28

FSB_IMPED_PCAL
FSB_IMPED_NCAL

OUT
OUT
OUT
OUT

5
5
5
5

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

GP_CP1_CLK_DP
GP_CP1_CLK_DN
GP_CP1_FLAG_DP
GP_CP1_FLAG_DN

AC33
AC34
Y29
Y30

FSB_GP_CP1_CLK_DP
FSB_GP_CP1_CLK_DN
FSB_GP_CP1_FLAG_DP
FSB_GP_CP1_FLAG_DN

OUT
OUT
OUT
OUT

5
5
5
5

GP_CP1_DATA0_DP
GP_CP1_DATA0_DN
GP_CP1_DATA1_DP
GP_CP1_DATA1_DN
GP_CP1_DATA2_DP
GP_CP1_DATA2_DN
GP_CP1_DATA3_DP
GP_CP1_DATA3_DN
GP_CP1_DATA4_DP
GP_CP1_DATA4_DN
GP_CP1_DATA5_DP
GP_CP1_DATA5_DN
GP_CP1_DATA6_DP
GP_CP1_DATA6_DN
GP_CP1_DATA7_DP
GP_CP1_DATA7_DN

AC28
AC29
AD29
AD30
AD34
AD33
AB29
AB30
AC32
AC31
AA29
AA30
AB33
AB34
AA34
AA33

FSB_GP_CP1_DATA0_DP
FSB_GP_CP1_DATA0_DN
FSB_GP_CP1_DATA1_DP
FSB_GP_CP1_DATA1_DN
FSB_GP_CP1_DATA2_DP
FSB_GP_CP1_DATA2_DN
FSB_GP_CP1_DATA3_DP
FSB_GP_CP1_DATA3_DN
FSB_GP_CP1_DATA4_DP
FSB_GP_CP1_DATA4_DN
FSB_GP_CP1_DATA5_DP
FSB_GP_CP1_DATA5_DN
FSB_GP_CP1_DATA6_DP
FSB_GP_CP1_DATA6_DN
FSB_GP_CP1_DATA7_DP
FSB_GP_CP1_DATA7_DN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

CP_GP1_CLK_DP
CP_GP1_CLK_DN
CP_GP1_FLAG_DP
CP_GP1_FLAG_DN

C2E4

IN

R2E5

0
402

2

.1UF 10%
6.3V
X5R
402

FSB_BYPCLK_DP
FSB_BYPCLK_DN
FSB_BYPCLK_SEL

FSB_CP_GP0_CLK_DP
FSB_CP_GP0_CLK_DN
FSB_CP_GP0_FLAG_DP
FSB_CP_GP0_FLAG_DN

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

V_GPUCORE

1

1

IC

1 OF 12

IN
IN
IN
IN

5
5
5
5

R5R2

U4D1

2

1

5%
CH

U2E2

R2R5

EMPTY

2

SN74LVC1G125
5
2
3

MEM_SCAN_EN_BUFF

VCC
IN
GND

OUT
OE_N

4
1

0
5%
CH
402

MEM_SCAN_EN
1

X801565-001

V_MEM

1

1

.1UF 10%
6.3V
X5R
402
13

IN

25
19
22

26
20
23

21
24

R4F8
1K
5%
CH
402

R2D11
1K
5%
CH
402

2

R2D12 2

0
402

2

OUT

1

2

C2R12

MEM SCAN BUFFERS
STUFFED
EMPTY
10K
0OHM

R2R5:

V_MEM

5%
CH

R5C11

2

1K
5%
EMPTY
402

FSB

5%
CH

U2D1

EMPTY

SN74LVC1G125

MEM_SCAN_TOP_EN_BUFF

5
2
3

VCC
IN
GND

OUT
OE_N

4
1

MEM_SCAN_TOP_EN
1

R4F7

X801565-001

2

OUT

19
25

21

23

OUT

20
26

22

24

1
1K
5%
CH
402

R2T2

2

1K
5%
CH
402

V_MEM

C4R70

X02125-001

1000PF
10%
50V
X7R
402

V_MEM

1

C2D5

1
0
402

2

.1UF 10%
6.3V
X5R
402

V_GPUCORE

13

FSB DECOUPLING

IN

R2R6

2

5%
CH

U2R1

1

EMPTY

SN74LVC1G125

MEM_SCAN_BOT_EN_BUFF

5
2
3

VCC
IN
GND

OUT
OE_N

1

R4U6

2
4
1

1K
5%
CH
402

R2T1

2

1K
5%
CH
402

MEM_SCAN_BOT_EN

X801565-001

C4R27
.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=GPU,

FSB]

C4R33
.1UF
10%
6.3V
X5R
402

C4R45
.1UF
10%
6.3V
X5R
402

C4T22
.1UF
10%
6.3V
X5R
402

C5R18
.1UF
10%
6.3V
X5R
402

C4R65
.1UF
10%
6.3V
X5R
402

C4R60
.1UF
10%
6.3V
X5R
402

C4T13
.1UF
10%
6.3V
X5R
402

13

IN

DRAWING
FALCON_FABD
Tue May 08 18:24:13

GPU_SCAN_BUFF_EN_N

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
12/82

REV
1.0

CR-13

:

@FALCON_LIB.FALCON(SCH_1):PAGE13

GPU,

VIDEO
2 OF 12

U4D1
FT2P14
34

R5D1

562
402

27
27

PEX_SB_GPU_L1_DP
PEX_SB_GPU_L1_DN
PEX_SB_GPU_L0_DP
PEX_SB_GPU_L0_DN

IN
IN
IN
IN

2

PEX_PCAL

1%
CH

R5D2

1

V_GPUPCIE

2K
402

R4R3

1
1.47K
402

2

27
27
28
28
28
28

R5D2

R5D1

R4R3

2K, 1%
49.9,
1%

562,
1%
EMPTY

1.47K,
EMPTY

1

40.2
402

A25
A24

NB_CLK_DP
NB_CLK_DN

E11

RST_IN_N*

B27
A27
B23
A23

PEX_RX1_DP
PEX_RX1_DN
PEX_RX0_DP
PEX_RX0_DN

A28
B28
B21

PEX_PCAL
PEX_NCAL
PEX_ICAL

40.2,
240,

13

PIX_CLK_IN_DP
PIX_CLK_IN_DN

C22
C23
G14
G15

NB_THERMD_P
NB_THERMD_N
ED_THERMD_P
ED_THERMD_N

2

G16

R4R8

1
40.2
402

V_MEM

2

1.5K
1%
CH
402

SROM_SO

AG16
V8

GPU_TCLK
GPU_TDO
GPU_TDI
GPU_TMS
GPU_TRST
GPU_TRST_ED

MEM_CALA
MEM_CALB

E13
D12
E12
G12
G11
G13

34

OUT

PEX_GPU_SB_L1_DP_C

1

PEX_GPU_SB_L1_DN_C
PEX_GPU_SB_L0_DP_C
PEX_GPU_SB_L0_DN_C

GPU_PIX_CLK_1X
PIX_DATA<14..0>

B14
B17
A17
D16
B16
A16
D15
B15
A15
A14
D13
B13
A13
B12
A12
D11

14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

A11
B11

SROM_EN_PSRO_OUT
SROM_SI
SROM_SCLK
SROM_CS

G17
E16
E15
E14

28

OUT
OUT
V_MEM

OUT

33

58

C4D2

2

PEX_GPU_SB_L1_DN

OUT

33

58

28

1

2

PEX_GPU_SB_L0_DP

OUT

33

58

C4D7

2

PEX_GPU_SB_L0_DN

OUT

33

58

.1UF 10%
6.3V
X5R
402

R4D1

2

C4D3

.1UF 10%
6.3V
X5R
402

1
1K
5%
EMPTY
402
DB4D1

1

TP

1

R4D2

GPU_VSYNC_OUT
GPU_HSYNC_OUT

VSYNC_OUT
HSYNC_OUT

PEX_GPU_SB_L1_DP

2

.1UF 10%
6.3V
X5R
402

28
OUT
28
OUT
GPU_SROM_EN_PSRO_OUT
GPU_SPI_SO
GPU_SPI_CLK
GPU_SPI_CS_N

2

1K
5%
CH
402

13
13
13

OUT
OUT
OUT

TCLK
TDO
TDI
TMS
TRST
TRST_ED

MEM_RST
MEM_SCAN_EN_BUFF
MEM_SCAN_TOP_EN_BUFF
MEM_SCAN_BOT_EN_BUFF

AG11
AN13
G9
G10

MEM_RST
MEM_SCAN_EN
MEM_SCAN_OEN_A
MEM_SCAN_OEN_B

OUT
OUT
OUT
OUT
2

1

20

19
12
12
12

21

22

23

24

25

26

2

R2E1

X02125-001

1

R2E2

B26
A26
B22
A22

C4D1

.1UF 10%
6.3V
X5R
402

MEM_CALB

1%
CH

V_MEM

1

FTP FT2P13

GPU_RST_DONE

D14

PIX_DATA14
PIX_DATA13
PIX_DATA12
PIX_DATA11
PIX_DATA10
PIX_DATA9
PIX_DATA8
PIX_DATA7
PIX_DATA6
PIX_DATA5
PIX_DATA4
PIX_DATA3
PIX_DATA2
PIX_DATA1
PIX_DATA0

MEM_CALA

1%
CH

1

1

1

D10
C10

34

GPU_SPI_SI

IN

IC

RST_DONE

1%
1%

IN

+ EEPROM + JTAG

1

PEX_TX1_DP
PEX_TX1_DN
PEX_TX0_DP
PEX_TX0_DN

R4R8
1%
1%

VERSION

PIX_CLK_OUT

GPU_TCLK_R

1%
CH

R4T1

1

R4T1
1% 40.2,
240,

R3C28 2

1.27K
402

1K
5%
CH
402

R4F6

1

1K
5%
CH
402

R2E4
J2D2
2X4HDR

1
3
5
7

2

1.5K
1%
CH
402

J5C2

HDR

2X3HDR

V_1P8
1
3
5

2
4
6
8

1

R2D10

PEX_NCAL

ANA_PIX_CLK_2X_DP
ANA_PIX_CLK_2X_DN
GPU_TEMP_P
GPU_TEMP_N
EDRAM_TEMP_P
EDRAM_TEMP_N

IN
IN
IN
OUT
IN
OUT

B13L
GUNGA

2

2

1%
CH

PEX_ICAL

1%
CH

GPU

2

GPU Y2

GPU_CLK_DP
GPU_CLK_DN

IN
IN

GPU_RST_N

IN
33
33
33
33

1

1

FTP

+ PCIEX

2
4
6

GPU_SPI_SI
GPU_SPI_WP_N

13
13

OUT
OUT

V_1P8

1
1

2

1.5K
1%
CH
402

R2E3

2

1.5K
1%
CH
402

2

13

13

IN

GPU_SPI_CLK

IN

GPU_SPI_SO

IN

GPU_SPI_CS_N

10K
5%
CH
402

2

R5P3
10K
5%
CH
402

+ PCIEX

5%
CH

R5C8
5%
CH

5%
CH

2

EMPTY
AT25020A

GPU_SPI_CLK_R
GPU_SPI_SO_R

GPU_SPI_CS_N_R

6
5

SCK
SDI

7
1
3

HOLD_N*
CS_N*
WP_N*

VCC

8

SDO

2

GND

4

C5C3

V_MEM

.1UF
10%
6.3V
X5R
402

VIDEO

GPU_SPI_SI

OUT
2

V_1P8

R4C6

R4C3
1K
402

1

R5C10

12

VIDEO

R5C5

1K
402

2

[PAGE_TITLE=GPU,

1
V_1P8

1K
402

1

OUT

10K
5%
CH
402

U4C1
13

GPU_SCAN_BUFF_EN_N

HDR

R4C7

1

R2D9

1.5K
1%
CH
402

X800552-001

2
10K
402

2
10K
402

R4C4

1

5%
CH

R4C5

1
1

5%
EMPTY

+ EEPROM + JTAG]

GPU_SPI_WP_N

IN

13

C3C2
4.7UF
10%
6.3V
X5R
805

DECOUPLING

C3R9
.1UF
10%
6.3V
X5R
402

C4R26
.1UF
10%
6.3V
X5R
402

C3R8
.1UF
10%
6.3V
X5R
402

10K
5%
CH
402

13

DRAWING
FALCON_FABD
Tue May 08 18:24:13

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
13/82

REV
1.0

CR-14

:

@FALCON_LIB.FALCON(SCH_1):PAGE14

GPU,
U4D1

20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_WDQS2
MA_RDQS2
MA_DM2

AP15
AN15
AM15
AN14
AN16
AL13
AP17
AM13
AP14
AL15
AP16

MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_WDQS2
MA_RDQS2
MA_DM2

20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ12
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1

AH16
AK20
AK16
AH20
AH17
AJ19
AJ18
AH18
AK19
AK17
AM17

MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ12
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1

20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19
20 19

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0

AK15
AH11
AH15
AK11
AH13
AK12
AJ13
AH12
AM12
AJ14
AK14

MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0

AK6
AP13

MA_VREF1
MA_VREF0

V_MEM

AP19
AN19
AL18
AN20
AN18
AM20
AN17
AL20
AP20
AM18
AP18

MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_DQ27
MA_DQ26
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DM3

1
549
1%
CH
402

2

.1UF
10%
6.3V
X5R
402

2

AH10
AK10
AN12
AP12

MA_A12
MA_A11
MA_A10
MA_A9
MA_A8
MA_A7
MA_A6
MA_A5
MA_A4
MA_A3
MA_A2
MA_A1
MA_A0

AN4
AP7
AP4
AP8
AN11
AP9
AN10
AP11
AN9
AN8
AN7
AN5
AP6

MA_BA2
MA_BA1
MA_BA0

AP10
AM10
AP5

MA_CKE
MA_WE_N*
MA_CAS_N*
MA_RAS_N*
MA_CS1_N*
MA_CS0_N*

AN6
AJ9
AK8
AK7
AK9
AL10

MA_CLK1_DP
MA_CLK1_DN
MA_CLK0_DP
MA_CLK0_DN
MA_A<12..0>

OUT
OUT
OUT
OUT
OUT

12
11
10
9
8
7
6
5
4
3
2
1
0

MA_BA<2..0>

2
1
0

MA_CKE
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS1_N
MA_CS0_N

OUT

OUT
OUT
OUT
OUT
OUT
OUT

19
19
19
19
19
19

20
20
19
19
19

19

20

20

20
20
20
20
20

21
21
21
21
21
21
21
21
21
21
21

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

22
22
22
22
22
22
22
22
22
22
22

21
21
21
21
21
21
21
21
21
21
21

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MB_DQ23
MB_DQ22
MB_DQ21
MB_DQ20
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DM2

AM23
AP23
AL23
AN23
AN25
AP22
AP25
AN21
AN22
AP24
AN24

MB_DQ23
MB_DQ22
MB_DQ21
MB_DQ20
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DM2

22
22
22
22
22
22
22
22
22
22
22

21
21
21
21
21
21
21
21
21
21
21

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_WDQS1
MB_RDQS1
MB_DM1

AH26
AN32
AK26
AN31
AN29
AN30
AK28
AK29
AK30
AN28
AK27

MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_WDQS1
MB_RDQS1
MB_DM1

22
22
22
22
22
22
22
22
22
22
22

21
21
21
21
21
21
21
21
21
21
21

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0

AK25
AH21
AH25
AK21
AH23
AK22
AJ23
AH22
AM22
AJ24
AK24

MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0

AG33
AP21

MB_VREF1
MB_VREF0

V_MEM

MA_VREF1

1

IC
1

MB_CLK1_DP
MB_CLK1_DN
MB_CLK0_DP
MB_CLK0_DN

2

1.27K
1%
CH
402

MB_A12
MB_A11
MB_A10
MB_A9
MB_A8
MB_A7
MB_A6
MB_A5
MB_A4
MB_A3
MB_A2
MB_A1
MB_A0

AK32
AE29
AE34
AJ30
AK33
AJ33
AK34
AM32
AJ34
AE30
AF28
AE33
AF29

MB_BA2
MB_BA1
MB_BA0

AH30
AH33
AG30

MB_CKE
MB_WE_N*
MB_CAS_N*
MB_RAS_N*
MB_CS1_N*
MB_CS0_N*

AG34
AF33
AF32
AF31
AH34
AF34

2

1
MEMORY CONTROLLER A,

DECOUPLING
2

2

TO CHANGE GPU VREF, CHANGE THESE RESISTORS
R4T3,
R4T6,
R5E1, R4T5,
R4R5, R4R2, R4T2,
VALUE

[PAGE_TITLE=GPU,

1.27K
1%
CH
402

1
2

C4T45
.1UF
10%
6.3V
X5R
402

TO MATCH THE TABLE
R4R7

THESE ARE THE GPU VREFS NEEDED
FOR VARIOUS MEMORIES.
CONSULT
WITH MEM TEAM FOR USAGE.

C4R3
4.7UF
10%
6.3V
X5R
805

C4T29
.22UF
10%
6.3V
X5R
402

C4T32

C4T42

.22UF
10%
6.3V
X5R
402

.22UF
10%
6.3V
X5R
402

C4T44

1

R5E1

C5E1
.1UF
10%
6.3V
X5R
402

2

1.27K
1%
CH
402

2

.22UF
10%
6.3V
X5R
402

C4T27
.22UF
10%
6.3V
X5R
402

C4T41
.22UF
10%
6.3V
X5R
402

12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0

MB_BA<2..0>

MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS1_N
MB_CS0_N

OUT
OUT
OUT
OUT
OUT

22
22
21
21

21

22

OUT

OUT
OUT
OUT
OUT
OUT
OUT

21
21
21
21
21
21

21

22

22
22
22
22
22

MEMORY CONTROLLER B,

DECOUPLING

C4T47

549
1%
CH
402

4.7UF
10%
6.3V
X5R
805

C4T31
.22UF
10%
6.3V
X5R
402

C4T34
.22UF
10%
6.3V
X5R
402

C5T2
.22UF
10%
6.3V
X5R
402

C4T39
.22UF
10%
6.3V
X5R
402

MB_VREF0

1

.22UF
10%
6.3V
X5R
402

R4T5

2

C4T35

MB_CLK1_DP
MB_CLK1_DN
MB_CLK0_DP
MB_CLK0_DN
MB_A<12..0>

1

R4T8

V_MEM

MA_VREF0

R4T6

V_MEM
MB_VREF1

549
1%
CH
402

AM33
AM34
AL33
AL34

V_MEM

549
1%
CH
402

R4T7

RESISTOR
1.27KOHM
1.40KOHM
1.47KOHM
1.54KOHM

MB_DQ31
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_RDQS3
MB_DM3

VERSION

X02125-001

1

1

MEM VREF
70%
72%
73%
74%

MA_CLK1_DP
MA_CLK1_DN
MA_CLK0_DP
MA_CLK0_DN

22
22
22
22
22
22
22
22
22
22
22

AN27
AP28
AP27
AP29
AL25
AP31
AM25
AP32
AP30
AN26
AP26

R5E2

R4T3

C4T40

4 OF 12
GPU Y2

MB_DQ31
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_RDQS3
MB_DM3

V_MEM

1

1

U4D1

1

X02125-001

R4T4

2

VERSION

A & B

IC

3 OF 12
GPU Y2

MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_DQ27
MA_DQ26
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DM3

MEMORY CONTROLLER 0 PARTITION

1.27K
1%
CH
402

1
2

C4T46

.1UF
10%
6.3V
X5R
402

C4T33
.22UF
10%
6.3V
X5R
402

C5T3
.22UF
10%
6.3V
X5R
402

C5T4
.22UF
10%
6.3V
X5R
402

C5T1

.22UF
10%
6.3V
X5R
402

C4T43
.22UF
10%
6.3V
X5R
402

MEMORY CONTROLLER A + B]

DRAWING
FALCON_FABD
Tue May 08 18:24:14

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
14/82

REV
1.0

CR-15

:

@FALCON_LIB.FALCON(SCH_1):PAGE15

GPU,
U4D1

GPU Y2
24
24
24
24
24
24
24
24
24
24
24

23
23
23
23
23
23
23
23
23
23
23

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3

R1
R3
R2
R4
N4
T2
N3
U1
T1
P2
P1

MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3

24
24
24
24
24
24
24
24
24
24
24

23
23
23
23
23
23
23
23
23
23
23

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2

L1
K4
L2
K3
N2
K2
N1
J2
K1
M1
M2

MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2

24
24
24
24
24
24
24
24
24
24
24

23
23
23
23
23
23
23
23
23
23
23

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1

J6
N6
J5
N7
L5
M5
L7
M3
M7
K5
K7

MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1

24
24
24
24
24
24
24
24
24
24
24

23
23
23
23
23
23
23
23
23
23
23

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0

H2
B2
H5
C2
F2
E5
F5
E2
D2
G5
G2

MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0

G1
E10

V_MEM
2

1 PARTITION

U4D1

MC_CLK1_DP
MC_CLK1_DN
MC_CLK0_DP
MC_CLK0_DN

MC_CLK1_DP
MC_CLK1_DN
MC_CLK0_DP
MC_CLK0_DN
MC_A<12..0>

J1
H1
F1
E1

MC_A12
MC_A11
MC_A10
MC_A9
MC_A8
MC_A7
MC_A6
MC_A5
MC_A4
MC_A3
MC_A2
MC_A1
MC_A0

A10
A7
B10
B6
D1
A5
A4
C1
B5
A6
B7
A9
B8

MC_BA2
MC_BA1
MC_BA0

B4
A3
B9

MC_CKE
MC_WE_N*
MC_CAS_N*
MC_RAS_N*
MC_CS1_N*
MC_CS0_N*

A8
E7
E8
E9
E6
B3

12
11
10
9
8
7
6
5
4
3
2
1
0

MC_BA<2..0>

2
1
0

MC_CKE
MC_WE_N
MC_CAS_N
MC_RAS_N
MC_CS1_N
MC_CS0_N

24
24
23
23

OUT
OUT
OUT
OUT
OUT

23

OUT

23
23
23
23
23
23

OUT
OUT
OUT
OUT
OUT
OUT

23

24

24

24
24
24
24
24

25
25
25
25
25
25
25
25
25
25
25

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MD_DQ31
MD_DQ30
MD_DQ29
MD_DQ28
MD_DQ27
MD_DQ26
MD_DQ25
MD_DQ24
MD_WDQS3
MD_RDQS3
MD_DM3

AC3
AC4
AC1
AD1
AB1
AE2
AA2
AE1
AD2
AC2
AB2

MD_DQ31
MD_DQ30
MD_DQ29
MD_DQ28
MD_DQ27
MD_DQ26
MD_DQ25
MD_DQ24
MD_WDQS3
MD_RDQS3
MD_DM3

26
26
26
26
26
26
26
26
26
26
26

25
25
25
25
25
25
25
25
25
25
25

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MD_DQ23
MD_DQ22
MD_DQ21
MD_DQ20
MD_DQ19
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_DM2

W2
W1
Y2
V4
Y4
V1
AA1
V2
V3
Y1
Y3

MD_DQ23
MD_DQ22
MD_DQ21
MD_DQ20
MD_DQ19
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_DM2

26
26
26
26
26
26
26
26
26
26
26

25
25
25
25
25
25
25
25
25
25
25

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1

W6
AC7
W5
AC6
AA5
AB5
AA7
AB3
AB7
Y5
Y7

MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1

26
26
26
26
26
26
26
26
26
26
26

25
25
25
25
25
25
25
25
25
25
25

BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT

MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_WDQS0
MD_RDQS0
MD_DM0

V7
P6
V6
P5
U3
R5
T5
T7
R7
U5
U7

MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_WDQS0
MD_RDQS0
MD_DM0

1

V_MEM
2

2

2

R4R5

2

1.27K
1%
CH
402

1

549
1%
CH
402

1
MEMORY CONTROLLER C,

DECOUPLING
2

MC_VREF0

1

R4R2

2

1.27K
1%
CH
402

1
2

1
C4R10
.1UF
10%
6.3V
X5R
402

2

C3R5

4.7UF
10%
6.3V
X5R
805

1
2

1
C4R38
.22UF
10%
6.3V
X5R
402

2

1

C4R51
.22UF
10%
6.3V
X5R
402

2

C4T14
.22UF
10%
6.3V
X5R
402

1

2

C4R48
.22UF
10%
6.3V
X5R
402

.1UF
10%
6.3V
X5R
402

2

1
TO CHANGE GPU VREF, CHANGE THESE RESISTORS
R4T3,
R4T6,
R5E1, R4T5,
R4R5, R4R2, R4T2,
RESISTOR VALUE
1.27KOHM
1.40KOHM
1.47KOHM
1.54KOHM

PAGE_TITLE=[GPU,

TO MATCH THE TABLE
R4R7

2

1
C4R23

1
C4R66

2

2

.22UF
10%
6.3V
X5R
402

.22UF
10%
6.3V
X5R
402

C4T12
.22UF
10%
6.3V
X5R
402

1

2

MD_A12
MD_A11
MD_A10
MD_A9
MD_A8
MD_A7
MD_A6
MD_A5
MD_A4
MD_A3
MD_A2
MD_A1
MD_A0

AK5
AL2
AM2
AF5
AE5
AF2
AF7
AE7
AG2
AM1
AJ2
AM3
AK2

MD_BA2
MD_BA1
MD_BA0

AG5
AH2
AJ5

MD_CKE
MD_WE_N*
MD_CAS_N*
MD_RAS_N*
MD_CS1_N*
MD_CS0_N*

AK1
AH1
AJ1
AL1
AH5
AG1

OUT
OUT
OUT
OUT
OUT

12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0

MD_BA<2..0>

MD_CKE
MD_WE_N
MD_CAS_N
MD_RAS_N
MD_CS1_N
MD_CS0_N

OUT

OUT
OUT
OUT
OUT
OUT
OUT

25
25
25
25
25
25

25

26
26
25
25
25

26

26

26
26
26
26
26

MEMORY CONTROLLER D,
R4R6

1.27K
1%
CH
402

DECOUPLING

1

R4T2

C4T36

MD_CLK1_DP
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN
MD_A<12..0>

AD6
AD5
AE4
AE3

V_MEM

V_MEM

2

1

549
1%
CH
402

1

C4T28
4.7UF
10%
6.3V
X5R
805

2

2

1
C4R15
.22UF
10%
6.3V
X5R
402

2

C4R61
.22UF
10%
6.3V
X5R
402

1
2

C4T38
.22UF
10%
6.3V
X5R
402

1

2

C4R50
.22UF
10%
6.3V
X5R
402

MD_VREF0

1

R4R7

2

GPU MEM VREF
70%
72%
73%
74%

MD_CLK1_DP
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN

X02125-001
549
1%
CH
402

1

V_MEM

1

MD_VREF1
MD_VREF0

MD_VREF1

R4R1
.1UF
10%
6.3V
X5R
402

VERSION

R3T2

549
1%
CH
402

1

C4R25

AF1
U2

V_MEM

IC

6 OF 12
GPU Y2

26
26
26
26
26
26
26
26
26
26
26

MC_VREF1
MC_VREF0

MC_VREF1

1

C & D

1

X02125-001

R4R4

1

VERSION

MEMORY CONTROLLER

IC

5 OF 12

1.27K
1%
CH
402

1
2

C4R64

1

.1UF
10%
6.3V
X5R
402

2

C4T7

.22UF
10%
6.3V
X5R
402

1
2

C4R31
.22UF
10%
6.3V
X5R
402

1
2

1
C4R12
.22UF
10%
6.3V
X5R
402

2

C4R19
.22UF
10%
6.3V
X5R
402

C4R32
.22UF
10%
6.3V
X5R
402

THESE ARE THE GPU VREFS NEEDED
FOR VARIOUS MEMORIES.
CONSULT
WITH MEM TEAM FOR USAGE.

MEMORY CONTROLLER

C + D]

DRAWING
FALCON_FABD
Tue May 08 18:24:14

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
15/82

REV
1.0

CR-16

:

@FALCON_LIB.FALCON(SCH_1):PAGE16

GPU,

PLL

POWER + FSB POWER

V_GPUCORE
FB4D1
1
120
0.2A
0.5
DCR

2
FB
603

1

C4D6
2.2UF
10%
6.3V
X5R
603

2

1
2

C4D5

.1UF
10%
6.3V
X5R
402

1
2

C4D4

0.01UF
10%
16V
X7R
402

V_GPUCORE
V_GPUPCIE

U4D1

GPU Y2

FB4T1
1
120
0.2A
0.5
DCR

2
V_PVDDA

FB
603

1

C4T48
2.2UF
10%
6.3V
X5R
603

2

1
2

1
C4T30

.1UF
10%
6.3V
X5R
402

C5R7

C4T37
0.01UF
10%
16V
X7R
402

2

.1UF
10%
6.3V
X5R
402

V_PVDDA_MEM

FB4R1
1
0.5

120
0.2A
DCR

8 OF 12

2

V_PVDDA_ED

FB
603

1
2

C4R68
2.2UF
10%
6.3V
X5R
603

1
2

C4R4
.1UF
10%
6.3V
X5R
402

C4R6

0.01UF
10%
16V
X7R
402

V_PVDDA_FSB

1
2

C4R8

.1UF
10%
6.3V
X5R
402

A20
A21

PVDDA
PVSSA

C27
C26

VDD_BSB1
VSS_BSB1

C25
C24

VDD_BSB0
VSS_BSB0

AG10
AG9

PVDDA_MEM
PVSSA_MEM

A18
A19

PVDDA_ED
PVSSA_ED

B25
B24

PVDDA_PEX
PVSSA_PEX

G34
F34

PVDDA_FSB
PVSSA_FSB

V_GPUPCIE

VERSION

IC
1
VDD_FSB24
VDD_FSB23
VDD_FSB22
VDD_FSB21
VDD_FSB20
VDD_FSB19
VDD_FSB18
VDD_FSB17
VDD_FSB16
VDD_FSB15
VDD_FSB14
VDD_FSB13
VDD_FSB12
VDD_FSB11
VDD_FSB10
VDD_FSB9
VDD_FSB8
VDD_FSB7
VDD_FSB6
VDD_FSB5
VDD_FSB4
VDD_FSB3
VDD_FSB2
VDD_FSB1
VDD_FSB0

AA27
AB28
AB32
AC27
AD28
AD31
K28
K31
L27
M28
M32
N27
P28
P31
R28
R32
T27
U28
U31
V27
V30
W28
W32
Y28
Y31

X02125-001

1
2

C4R5

C4R7

.1UF
10%
6.3V
X5R
402

0.01UF
10%
16V
X7R
402

C5R13

C5R15

FB5R1
1
120
0.2A
0.5
DCR

2
FB
603

1
2

[PAGE_TITLE=GPU,

C5R19
2.2UF
10%
6.3V
X5R
603

PLL

1
2

.1UF
10%
6.3V
X5R
402

0.01UF
10%
16V
X7R
402

POWER + FSB POWER]

DRAWING
FALCON_FABD
Tue May 08 18:24:14

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
16/82

REV
1.0

CR-17

:

@FALCON_LIB.FALCON(SCH_1):PAGE17

GPU,
V_GPUCORE

CORE POWER + MEM POWER

V_GPUCORE
IC

U4D1
U4D1
E28
D27
E27
D26
E26
G26
G25
D24
E24
E23
G24
D23
G23
F22
G22
G21
D29
E25
AA14
AA15
AA16
AA19
AA20
AA21
AB11
AB12
AB13
AB17
AB18
AB22
AB23
AB24
AC11
AC12
AC13
AC17
AC18
AC22
AC23
AC24
AD11
AD12
AD13
AD17
AD18
AD22
AD23
AD24
B18
B20
C19
C21
C29
C31
C33
C34
D17
D18
D20
D22
D30
D32
D34
E17
E19
E21
E31
F17
F18
F20
F23
F25
F27
F29
F30
G19
G28
G32
H12

9 OF 12

GPU Y2
VDD_CORE157
VDD_CORE156
VDD_CORE155
VDD_CORE154
VDD_CORE153
VDD_CORE152
VDD_CORE151
VDD_CORE150
VDD_CORE149
VDD_CORE148
VDD_CORE147
VDD_CORE146
VDD_CORE145
VDD_CORE144
VDD_CORE143
VDD_CORE142
VDD_CORE141
VDD_CORE140
VDD_CORE139
VDD_CORE138
VDD_CORE137
VDD_CORE136
VDD_CORE135
VDD_CORE134
VDD_CORE133
VDD_CORE132
VDD_CORE131
VDD_CORE130
VDD_CORE129
VDD_CORE128
VDD_CORE127
VDD_CORE126
VDD_CORE125
VDD_CORE124
VDD_CORE123
VDD_CORE122
VDD_CORE121
VDD_CORE120
VDD_CORE119
VDD_CORE118
VDD_CORE117
VDD_CORE116
VDD_CORE115
VDD_CORE114
VDD_CORE113
VDD_CORE112
VDD_CORE111
VDD_CORE110
VDD_CORE109
VDD_CORE108
VDD_CORE107
VDD_CORE106
VDD_CORE105
VDD_CORE104
VDD_CORE103
VDD_CORE102
VDD_CORE101
VDD_CORE100
VDD_CORE99
VDD_CORE98
VDD_CORE97
VDD_CORE96
VDD_CORE95
VDD_CORE94
VDD_CORE93
VDD_CORE92
VDD_CORE91
VDD_CORE90
VDD_CORE89
VDD_CORE88
VDD_CORE87
VDD_CORE86
VDD_CORE85
VDD_CORE84
VDD_CORE83
VDD_CORE82
VDD_CORE81
VDD_CORE80
VDD_CORE79

VERSION 1
VDD_CORE78
VDD_CORE77
VDD_CORE76
VDD_CORE75
VDD_CORE74
VDD_CORE73
VDD_CORE72
VDD_CORE71
VDD_CORE70
VDD_CORE69
VDD_CORE68
VDD_CORE67
VDD_CORE66
VDD_CORE65
VDD_CORE64
VDD_CORE63
VDD_CORE62
VDD_CORE61
VDD_CORE60
VDD_CORE59
VDD_CORE58
VDD_CORE57
VDD_CORE56
VDD_CORE55
VDD_CORE54
VDD_CORE53
VDD_CORE52
VDD_CORE51
VDD_CORE50
VDD_CORE49
VDD_CORE48
VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39
VDD_CORE38
VDD_CORE37
VDD_CORE36
VDD_CORE35
VDD_CORE34
VDD_CORE33
VDD_CORE32
VDD_CORE31
VDD_CORE30
VDD_CORE29
VDD_CORE28
VDD_CORE27
VDD_CORE26
VDD_CORE25
VDD_CORE24
VDD_CORE23
VDD_CORE22
VDD_CORE21
VDD_CORE20
VDD_CORE19
VDD_CORE18
VDD_CORE17
VDD_CORE16
VDD_CORE15
VDD_CORE14
VDD_CORE13
VDD_CORE12
VDD_CORE11
VDD_CORE10
VDD_CORE9
VDD_CORE8
VDD_CORE7
VDD_CORE6
VDD_CORE5
VDD_CORE4
VDD_CORE3
VDD_CORE2
VDD_CORE1
VDD_CORE0

11
H14
H16
H18
H20
H22
H24
H26
H27
J27
L11
L12
L13
L17
L18
L22
L23
L24
M11
M12
M13
M17
M18
M22
M23
M24
N11
N12
N13
N17
N18
N22
N23
N24
P14
P15
P16
P19
P20
P21
R14
R15
R16
R19
R20
R21
T14
T15
T16
T19
T20
T21
U11
U12
U13
U17
U18
U22
U23
U24
V11
V12
V13
V17
V18
V22
V23
V24
W14
W15
W16
W19
W20
W21
Y14
Y15
Y16
Y19
Y20
Y21

V_MEM

V_MEM
U4D1

AA4
AA6
AB6
AC5
AC8
AD4
AD7
AE8
AE28
AE31
AF3
AF6
AF27
AF30
AG4
AG7
AG13
AG15
AG17
AG20
AG23
AG25
AG28
AG32
AH3
AH6
AH8
AH9
AH14
AH19
AH24
AH27
AH29
AH31
AJ4
AJ7
AJ11
AJ12
AJ16
AJ21
AJ22
AJ26
AJ28
AJ32
AK3
AK13
AK23
AK31
AL4
AL6
AL8
AL11
AL14
AL17
AL21
AL24

10

GPU Y2
VDD_MEM111
VDD_MEM110
VDD_MEM109
VDD_MEM108
VDD_MEM107
VDD_MEM106
VDD_MEM105
VDD_MEM104
VDD_MEM103
VDD_MEM102
VDD_MEM101
VDD_MEM100
VDD_MEM99
VDD_MEM98
VDD_MEM97
VDD_MEM96
VDD_MEM95
VDD_MEM94
VDD_MEM93
VDD_MEM92
VDD_MEM91
VDD_MEM90
VDD_MEM89
VDD_MEM88
VDD_MEM87
VDD_MEM86
VDD_MEM85
VDD_MEM84
VDD_MEM83
VDD_MEM82
VDD_MEM81
VDD_MEM80
VDD_MEM79
VDD_MEM78
VDD_MEM77
VDD_MEM76
VDD_MEM75
VDD_MEM74
VDD_MEM73
VDD_MEM72
VDD_MEM71
VDD_MEM70
VDD_MEM69
VDD_MEM68
VDD_MEM67
VDD_MEM66
VDD_MEM65
VDD_MEM64
VDD_MEM63
VDD_MEM62
VDD_MEM61
VDD_MEM60
VDD_MEM59
VDD_MEM58
VDD_MEM57
VDD_MEM56

OF 12

IC

VERSION 1
VDD_MEM55
VDD_MEM54
VDD_MEM53
VDD_MEM52
VDD_MEM51
VDD_MEM50
VDD_MEM49
VDD_MEM48
VDD_MEM47
VDD_MEM46
VDD_MEM45
VDD_MEM44
VDD_MEM43
VDD_MEM42
VDD_MEM41
VDD_MEM40
VDD_MEM39
VDD_MEM38
VDD_MEM37
VDD_MEM36
VDD_MEM35
VDD_MEM34
VDD_MEM33
VDD_MEM32
VDD_MEM31
VDD_MEM30
VDD_MEM29
VDD_MEM28
VDD_MEM27
VDD_MEM26
VDD_MEM25
VDD_MEM24
VDD_MEM23
VDD_MEM22
VDD_MEM21
VDD_MEM20
VDD_MEM19
VDD_MEM18
VDD_MEM17
VDD_MEM16
VDD_MEM15
VDD_MEM14
VDD_MEM13
VDD_MEM12
VDD_MEM11
VDD_MEM10
VDD_MEM9
VDD_MEM8
VDD_MEM7
VDD_MEM6
VDD_MEM5
VDD_MEM4
VDD_MEM3
VDD_MEM2
VDD_MEM1
VDD_MEM0

X02125-001

X02125-001

[PAGE_TITLE=GPU,

IC

U4D1

IC

CORE POWER + MEM POWER]

AL28
AL30
AL32
AM5
AM7
AM9
AM16
AM19
AM26
AM27
AM29
AM31
AN2
AP3
C3
C5
C7
C9
C12
C14
C16
C18
D4
D6
D8
E3
F4
F7
F9
F11
F13
F15
G3
G6
G8
H4
H7
H10
J3
J7
K8
L4
L6
M6
N5
N8
P4
P7
R8
T3
T6
U4
U8
W3
W7
Y8

GPU Y2
A1
AA3
AA8
AA11
AA12
AA13
AA17
AA18
AA22
AA23
AA24
AB4
AB8
AB14
AB15
AB16
AB19
AB20
AB21
AB27
AB31
AC14
AC15
AC16
AC19
AC20
AC21
AC30
AD3
AD8
AD14
AD15
AD16
AD19
AD20
AD21
AD27
AD32
AE6
AE27
AE32
AF4
AF8
AG3
AG6
AG8
AG12
AG14
AG18
AG19
AG21
AG22
AG24
AG26
AG27
AG29
AG31
AH4
AH7
AH28
AH32
AJ3
AJ6
AJ8
AJ10

VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

12

OF 12
VERSION

GPU Y2
1

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131

F21
F24
F26
F28
F31
G4
G7
G18
G20
G27
G29
G33
H3
H6
H8
H9
H11
H13
H15
H17
H19
H21
H23
H25
H28
J4
J8
J28
K6
K27
K32
L3
L8
L14
L15
L16
L19
L20
L21
L28
M4
M8
M14
M15
M16
M19
M20
M21
M27
M31
N14
N15
N16
N19
N20
N21
N28
N29
N30
P3
P8
P11
P12
P13
P17

AJ15
AJ17
AJ20
AJ25
AJ27
AJ29
AJ31
AK4
AK18
AL3
AL5
AL7
AL9
AL12
AL16
AL19
AL22
AL26
AL27
AL29
AL31
AM4
AM6
AM8
AM11
AM14
AM21
AM24
AM28
AM30
AN3
AN33
B19
B33
C4
C6
C8
C11
C13
C15
C17
C20
C28
C32
D3
D5
D7
D9
D19
D21
D31
E4
E18
E20
E22
E30
E32
F3
F6
F8
F10
F12
F14
F16
F19

X02125-001

OF 12
VERSION

VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66

1

VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS20
VSS21
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

P18
P22
P23
P24
P27
P32
R6
R11
R12
R13
R17
R18
R22
R23
R24
R27
R31
T4
T8
T11
T12
T13
T17
T18
T22
T23
T24
U6
U14
U15
U16
U19
U20
U21
U27
U32
V5
V14
V15
V16
V19
V20
V21
W4
W11
W8
W12
W13
W17
W18
W22
W23
W24
W27
W31
Y6
Y11
Y12
Y13
Y17
Y18
Y22
Y23
Y24
Y27
Y32

X02125-001

DRAWING
XENON_FABK
Tue May 08

18:24:14

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
17/82

REV
1.0

CR-18

:

@FALCON_LIB.FALCON(SCH_1):PAGE18

GPU,

DECOUPLING

V_GPUCORE

V_GPUCORE

V_GPUCORE

N:EMPTIES
1

C4R20

2

.1UF 10%
6.3V
X5R
402

1

C4R37

2

.1UF 10%
6.3V
X5R
402

1

C4T15

2

.1UF 10%
6.3V
X5R
402

1

C4R14

2

.1UF 10%
6.3V
X5R
402

1

C4R39

2

.1UF 10%
6.3V
X5R
402

1

C4T25

2

.1UF 10%
6.3V
X5R
402

1

C4T11

2

.1UF 10%
6.3V
X5R
402

C4T3

1

2

C4R49

2

.1UF 10%
6.3V
X5R
402

1

C4R18

2

.1UF 10%
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[PAGE_TITLE=GPU,

C4R11

2

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402

1

C4R17

2

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402

1

C4R55

2

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6.3V
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402

1

C4R47

2

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6.3V
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402

1

C4T20

2

.1UF 10%
6.3V
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402

1

C4R36

2

.1UF 10%
6.3V
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402

1

C4R34

2

.1UF 10%
6.3V
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402

1

.1UF 10%
6.3V
EMPTY
402

1

1

C4R42

2

.1UF 10%
6.3V
X5R
402

1

C4T16

2

.1UF 10%
6.3V
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402

1

C4T1

2

.1UF 10%
6.3V
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402

DECOUPLING]

1

C4R16

2

.1UF 10%
6.3V
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1

C4R21

2

.1UF 10%
6.3V
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1

C4T26

2

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6.3V
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1

C4T21

2

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6.3V
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1

C4R46

2

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6.3V
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1

C4R41

2

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1

C4R35

2

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2

C4R67

1

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1

C4R63

2

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1

C4T2

2

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1

C4R28

2

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1

C4R22

2

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1

C4T23

2

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1

C4R44

2

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1

C4T24

2

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1

C4T19

2

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1

C4T18

2

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1

C4R62

2

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1

C4R43

2

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1

C5R17

2

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1

C4R13

2

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1

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1

2

1

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2

C5R10

1

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1

C5R12

2

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1

C4R24

C4R40

1

C5R8

C4R9

1

C5R14

2

1

C5R9

2

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2

2

2

C4R57

1

C4R56

2

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1

C4T4

2

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1

C4R58

2

1

C4T8

2

2

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2

C6E2

C5R5

C5R4

1

C5R20

2

1

2

C5R2

1

C5R1

1

C5D3

1

2

C5D4

1

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2

1

C5D6

2

C4R29

1

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2

C4T17

1

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2

C4R30

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C4R69

1

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2

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1

1

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4.7UF 10%
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2

C6R47

4.7UF 10%
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4.7UF 10%
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C5D5

1

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1

4.7UF 10%
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2

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402

1

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2

2

C5D2

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2

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2

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402

C4T6

1

2

2

C4R59

1

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1

C4T5

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2

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402

2

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EMPTY
402

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6.3V
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402

1

2

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6.3V
EMPTY
402

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402

1

C4R54

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402

C5R3

1

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805

2

C5R11

1

4.7UF 10%
6.3V
X5R
805

2

C5R6

1

4.7UF 10%
6.3V
X5R
805

DRAWING
FALCON_FABD
Tue May 08 18:24:14

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
18/82

REV
1.0

CR-19

:

@FALCON_LIB.FALCON(SCH_1):PAGE19

MEMORY PARTITION
CHIP

V_MEM

1
60.4
1%
CH
402

2

14
13
14

2

V_MEM

60.4
1%
CH
402

U4F1

MA_CLK0_DN

IN
IN

MEM_RST
MA_A<11..0>

J11
J10

MA_BA<2..0>

IN

CLK_DP
CLK_DN

V9

RESET

11
10
9
8
7
6
5
4
3
2
1
0

L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4

A11/A7
A10/A8
A9/A3
A8/A10
A7/A11
A6/A2
A5/A1
A4/A0
A3/A9
A2/A6
A1/A5
A0/A4

2
1
0

H10
G9
G4

BA2/RAS_N
BA1/BA0
BA0/BA1

14
14
14
14
14

IN
IN
IN
IN
IN

MA_CKE
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS0_N

H4
H9
F4
H3
F9

CKE/WE_N
WE_N/CKE
CAS_N/CS_N
RAS_N/BA2
CS_N/CAS_N

12

IN

MEM_SCAN_TOP_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

19
20

IN
IN

MEM_A_VREF1
MEM_A_VREF0

H1
H12

U4F1

IC
GDDR136
MF=0

IN

14

TOP
= 0

R4F4

MA_CLK0_DP

IN

A,

MIRROR FUNCTION

1

R4F3

14

SELECT = 0,

VREF1
VREF0

V_MEM

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_DQ27
MA_DQ26
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_WDQS2
MA_RDQS2
MA_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ12
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

14
14
14
14
14
14
14
14

20
20
20
20
20
20
20
20
14
20 14
14

14
14
14
14
14
14
14
14

20
20
20
20
20
20
20
20
14
20 14
14

14
14
14
14
14
14
14
14

20
20
20
20
20
20
20
20
14
20 14
14

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN
14
14
14
14
14
14
14
14

IN
OUT
IN

20
20
20
20
20
20
20
20
14
20 14
14

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

IC
GDDR136
MF=0
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

X801995-011
MA_CS1_N

14

IN

MX_CS1_N CONNECTED
TO J3 O SUPPORT 1G
RAM CONFIGS.

MA_ZQ_TOP

1

R3F1

X801995-011

1

R4U4

2

549
1%
CH
402

2

243
1%
CH
402

PARTITION
MEM_A_VREF1

OUT

19

1
R4U5
1.27K
1%
CH
402

C4U9
.1UF
10%
6.3V
X5R
402

TO CHANGE MEM VREF, CHANGE THESE RESISTORS
R4U5, R4F2,
R5U3, R5F2,
R2R2, R3D2, R2T3,
MEM VREF
70%
72%

V_MEM
MEMORY A,

TOP,

DECOUPLING

20

1

2

A DECOUPLING
V_MEM

RESISTOR
1.27KOHM
1.40KOHM

TO MATCH THE TABLE
R3E2

2

C3F3

C4F12

.22UF
10%
6.3V
X5R
402

4.7UF
10%
6.3V
X5R
805

C4F9
.22UF
10%
6.3V
X5R
402

C4F11
.22UF
10%
6.3V
X5R
402

C4F7
.22UF
10%
6.3V
X5R
402

C3F1

.22UF
10%
6.3V
X5R
402

C4F1

.22UF
10%
6.3V
X5R
402

C4F6
.22UF
10%
6.3V
X5R
402

C4F3
.22UF
10%
6.3V
X5R
402

VALUE

THESE ARE THE MEM VREFS NEEDED
FOR VARIOUS MEMORIES.
CONSULT
WITH MEM TEAM FOR USAGE.

[PAGE_TITLE=DUAL

ETHERNET PHY]

DRAWING
FALCON_FABD
Tue May 08 18:24:15

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
19/82

REV
1.0

CR-20

:

@FALCON_LIB.FALCON(SCH_1):PAGE20

MEMORY PARTITION

V_MEM

CHIP

1

2

60.4
1%
CH
402

14
13
14

MA_CLK1_DN

IN
IN

MEM_RST
MA_A<11..0>

14

2

U4U1

J11
J10

11
10
9
8
7
6
5
4
3
2
1
0

MA_BA<2..0>

IN

IC

2
1
0

CLK_DP
CLK_DN

V9

RESET

L9
K11
M4
K2
L4
K3
H2
K4
M9
K10
H11
K9

A7/A11
A8/A10
A3/A9
A10/A8
A11/A7
A2/A6
A1/A5
A0/A4
A9/A3
A6/A2
A5/A1
A4/A0

H3
G4
G9

RAS_N/BA2
BA0/BA1
BA1/BA0

14
14
14
14
14

IN
IN
IN
IN
IN

MA_CKE
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS1_N

12

IN

MEM_SCAN_BOT_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

20
19

IN
IN

MEM_A_VREF0
MEM_A_VREF1

H9
H4
F9
H10
F4

WE_N/CKE
CKE/WE_N
CS_N/CAS_N
BA2/RAS_N
CAS_N/CS_N

H1
H12

VREF1
VREF0

V_MEM

V_MEM

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_WDQS2
MA_RDQS2
MA_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_DQ27
MA_DQ26
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ12
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

19
19
19
19
19
19
19
19
14
19 14
14

14
14
14
14
14
14
14
14

19
19
19
19
19
19
19
19
14
19 14
14

14
14
14
14
14
14
14
14

19
19
19
19
19
19
19
19
14
19 14
14

14
14
14
14
14
14
14
14

19
19
19
19
19
19
19
19
14
19 14
14

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

U4U1

549
1%
CH
402

2

MEM_A_VREF0

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

GDDR136
MF=1
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3
J3
J2

NC<1>
NC<0>

X801995-011

243
1%
CH
402

V_MEM
MEMORY A,

OUT

19

C3U2
.22UF
10%
6.3V
X5R
402

C4F2

.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=MEMORY

BOTTOM,

DECOUPLING

20

1
1.27K
1%
CH
402

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

R3U1

R4F1

R4F2

IC

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

1
X801995-011

2

14
14
14
14
14
14
14
14

MA_ZQ_BOT

1

2

= 1

60.4
1%
CH
402

GDDR136
MF=1

IN

BOTTOM

R4U3

MA_CLK1_DP

IN

A,

MIRROR FUNCTION

1

R4U2

14

SELECT = 1,

PARTITION

A,

TOP]

DRAWING
FALCON_FABD
Tue May 08 18:24:15

C4U8
.22UF
10%
6.3V
X5R
402

2007

C4U11
.22UF
10%
6.3V
X5R
402

C4U6
.22UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

C3U1
.22UF
10%
6.3V
X5R
402

C4U1
.22UF
10%
6.3V
X5R
402

C4U5
.22UF
10%
6.3V
X5R
402

PROJECT NAME
FALCON_RETAIL

C4U2
.22UF
10%
6.3V
X5R
402

PAGE
20/82

REV
1.0

CR-21

:

@FALCON_LIB.FALCON(SCH_1):PAGE21

MEMORY PARTITION
CHIP

V_MEM

1
60.4
1%
CH
402

R5F4

V_MEM

2

U5F1
IC
GDDR136
MF=0

MB_CLK0_DP

IN

14
13

MEM_RST
MB_A<11..0>

IN
IN

14

14

J11
J10

MB_CLK0_DN

IN

MB_BA<2..0>

IN

14
14
14
14
14

CLK_DP
CLK_DN

V9

RESET

11
10
9
8
7
6
5
4
3
2
1
0

L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4

A11/A7
A10/A8
A9/A3
A8/A10
A7/A11
A6/A2
A5/A1
A4/A0
A3/A9
A2/A6
A1/A5
A0/A4

2
1
0

H10
G9
G4

BA2/RAS_N
BA1/BA0
BA0/BA1

MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS0_N

IN
IN
IN
IN
IN

TOP
= 0

60.4
1%
CH
402

U5F1
14

B,

MIRROR FUNCTION

1

R5F3

2

SELECT = 0,

H4
H9
F4
H3
F9

CKE/WE_N
WE_N/CKE
CAS_N/CS_N
RAS_N/BA2
CS_N/CAS_N

12

IN

MEM_SCAN_TOP_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

21
22

IN
IN

MEM_B_VREF1
MEM_B_VREF0

H1
H12

VREF1
VREF0

V_MEM

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MB_DQ31
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_RDQS3
MB_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MB_DQ23
MB_DQ22
MB_DQ21
MB_DQ20
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_WDQS1
MB_RDQS1
MB_DM1

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

14
14
14
14
14
14
14
14

22
22
22
22
22
22
22
22
14
22 14
14

14
14
14
14
14
14
14
14

22
22
22
22
22
22
22
22
14
22 14
14

IN
OUT
IN

IN
OUT
IN
14
14
14
14
14
14
14
14

IN
OUT
IN
14
14
14
14
14
14
14
14

IN
OUT
IN

22
22
22
22
22
22
22
22
14
22 14
14
22
22
22
22
22
22
22
22
14
22 14
14

IC

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

GDDR136
MF=1
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3
J3
J2

NC<1>
NC<0>

X801995-011

MB_CS1_N

IN

14

MB_ZQ_TOP

1
1

2

R4F5

X801995-011

R5U4

549
1%
CH
402

2

MEM_B_VREF1

OUT

21

V_MEM

C4F10
1

R5U3

1.27K
1%
CH
402

C5U5

.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=MEMORY

2

PARITION

MEMORY B,

PARTITION
B DECOUPLING
V_MEM

22

1

2

243
1%
CH
402

A,

BOTTOM]

C5F6
4.7UF
10%
6.3V
X5R
805

1 C5F8
2

220UF
20%
10V
ELEC
RDL

.22UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:15

C5F5
.22UF
10%
6.3V
X5R
402

2007

C4F8
.22UF
10%
6.3V
X5R
402

TOP,

DECOUPLING

C4F5
.22UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

C4F4
.22UF
10%
6.3V
X5R
402

C5F2
.22UF
10%
6.3V
X5R
402

C5F3
.22UF
10%
6.3V
X5R
402

PROJECT NAME
FALCON_RETAIL

C5F4
.22UF
10%
6.3V
X5R
402

PAGE
21/82

REV
1.0

CR-22

:

@FALCON_LIB.FALCON(SCH_1):PAGE22

MEMORY PARTITION
CHIP

SELECT = 1,

B,

MIRROR FUNCTION

BOTTOM
= 1

V_MEM

1

1

R5U2
60.4
1%
CH
402

2
14

IN

R5U1
60.4
1%
CH
402

2

U5U1

IC
GDDR136
MF=1

MB_CLK1_DP

14
13
14

IN

MB_CLK1_DN

IN
IN

MEM_RST
MB_A<11..0>

14

IN

J11
J10
V9
11
10
9
8
7
6
5
4
3
2
1
0

MB_BA<2..0>

L9
K11
M4
K2
L4
K3
H2
K4
M9
K10
H11
K9
H3
G4
G9

2
1
0

CLK_DP
CLK_DN

RAS_N/BA2
BA0/BA1
BA1/BA0

IN
IN
IN
IN
IN

MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS1_N

12

IN

MEM_SCAN_BOT_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

22
21

IN
IN

MEM_B_VREF0
MEM_B_VREF1

14
14
14
14
14

H9
H4
F9
H10
F4

H1
H12

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MB_DQ23
MB_DQ22
MB_DQ21
MB_DQ20
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MB_DQ31
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_RDQS3
MB_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_WDQS1
MB_RDQS1
MB_DM1

ZQ

A4

RESET
A7/A11
A8/A10
A3/A9
A10/A8
A11/A7
A2/A6
A1/A5
A0/A4
A9/A3
A6/A2
A5/A1
A4/A0

WE_N/CKE
CKE/WE_N
CS_N/CAS_N
BA2/RAS_N
CAS_N/CS_N

VREF1
VREF0

V_MEM

V_MEM

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

14
14
14
14
14
14
14
14

IN
OUT
IN
14
14
14
14
14
14
14
14

21
21
21
21
21
21
21
21
14
21
14

14
14
14
14
14
14
14
14

21
21
21
21
21
21
21
21
14
21
14

14
14
14
14
14
14
14
14

21
21
21
21
21
21
21
21
14
21
14

IN
OUT
IN

BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN

21
21
21
21
21
21
21
21
14
21
14

U5U1

14

14

14

IC

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

GDDR136
MF=1
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

X801995-011

14

MB_ZQ_BOT

1
1

2

R4U1

X801995-011

R5F1
549
1%
CH
402

2

MEM_B_VREF0

OUT

21

243
1%
CH
402

V_MEM
MEMORY B,

22

1

R5F2

2

1.27K
1%
CH
402

[PAGE_TITLE=MEMORY

C4U10
.22UF
10%
6.3V
X5R
402

C5F1
.1UF
10%
6.3V
X5R
402

PARITION

B,

TOP]

DRAWING
FALCON_FABD
Tue May 08 18:24:15

2007

C5U4
.22UF
10%
6.3V
X5R
402

C4U7
.22UF
10%
6.3V
X5R
402

BOTTOM,

C4U4
.22UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

DECOUPLING

C4U3
.22UF
10%
6.3V
X5R
402

C5U1
.22UF
10%
6.3V
X5R
402

PROJECT NAME
FALCON_RETAIL

C5U2
.22UF
10%
6.3V
X5R
402

C5U3
.22UF
10%
6.3V
X5R
402

PAGE
22/82

REV
1.0

CR-23

:

@FALCON_LIB.FALCON(SCH_1):PAGE23

MEMORY PARTITION
CHIP

SELECT = 0,

C,

MIRROR FUNCTION

TOP
= 0

V_MEM

1

1

R3D5

2
15

60.4
1%
CH
402

R3D4

2

V_MEM

60.4
1%
CH
402

U3D1

IN

15
13

GDDR136
MF=0

15

IN

MC_CLK0_DN

IN
IN

MEM_RST
MC_A<11..0>

15

IN

J11
J10

MC_BA<2..0>

CLK_DP
CLK_DN

V9

RESET

11
10
9
8
7
6
5
4
3
2
1
0

L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4

A11/A7
A10/A8
A9/A3
A8/A10
A7/A11
A6/A2
A5/A1
A4/A0
A3/A9
A2/A6
A1/A5
A0/A4

2
1
0

H10
G9
G4

BA2/RAS_N
BA1/BA0
BA0/BA1

15
15
15
15
15

IN
IN
IN
IN
IN

MC_CKE
MC_WE_N
MC_CAS_N
MC_RAS_N
MC_CS0_N

H4
H9
F4
H3
F9

CKE/WE_N
WE_N/CKE
CAS_N/CS_N
RAS_N/BA2
CS_N/CAS_N

12

IN

MEM_SCAN_TOP_EN

A9

MF

MEM_SCAN_EN

V4

SCAN_EN

12

IN
23
24

IN
IN

MEM_C_VREF1
MEM_C_VREF0

H1
H12

VREF1
VREF0

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

V_MEM

15
15
15
15
15
15
15
15

24
24
24
24
24
24
24
24
15
24 15
15

15
15
15
15
15
15
15
15

24
24
24
24
24
24
24
24
15
24 15
15

15
15
15
15
15
15
15
15

24
24
24
24
24
24
24
24
15
24 15
15

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN
15
15
15
15
15
15
15
15

IN
OUT
IN

24
24
24
24
24
24
24
24
15
24 15
15

2

549
1%
CH
402

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

X801995-011

MC_CS1_N

243
1%
CH
402

IN

15

V_MEM
MEMORY C,

C2E1

OUT

23

24

1
1

[PAGE_TITLE=MEMORY

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

TOP,

DECOUPLING

PARTITION
C DECOUPLING
V_MEM
MEM_C_VREF1

2

V2
M12
M1
V11
F12
F1
A11
A2

GDDR136
MF=0

R3D1

R2R1

1.27K
1%
CH
402

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

1

1

R2R2

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

MC_ZQ_TOP

X801995-011

2

IC

IC

U3D1

MC_CLK0_DP

C2R9

2

.1UF
10%
6.3V
X5R
402

PARTITION

B,

BOTTOM]

C2D3
4.7UF
10%
6.3V
X5R
805

1
2

C3C5
4.7UF
10%
6.3V
X5R
805

1
2

C2E8

.22UF
10%
6.3V
X5R
402

C3E2

.22UF
10%
6.3V
X5R
402

C3E1

.22UF
10%
6.3V
X5R
402

C3E3

.22UF
10%
6.3V
X5R
402

C3E5
.22UF
10%
6.3V
X5R
402

C3E7
.22UF
10%
6.3V
X5R
402

C3E6
.22UF
10%
6.3V
X5R
402

C2E3

.22UF
10%
6.3V
X5R
402

4.7UF
10%
6.3V
X5R
805

DRAWING
FALCON_FABD
Tue May 08 18:24:15

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
23/82

REV
1.0

CR-24

:

@FALCON_LIB.FALCON(SCH_1):PAGE24

MEMORY PARTITION
CHIP

SELECT = 1,

C,

MIRROR FUNCTION

BOTTOM
= 1

V_MEM

1

1

R2R4

2
15

IN

60.4
1%
CH
402

R2R3

2

60.4
1%
CH
402

U3R1

15

IN

MC_CLK1_DN

13

IN
IN

MEM_RST
MC_A<11..0>

15

15

J11
J10

11
10
9
8
7
6
5
4
3
2
1
0

MC_BA<2..0>

IN

2
1
0

CLK_DP
CLK_DN

V9

RESET

L9
K11
M4
K2
L4
K3
H2
K4
M9
K10
H11
K9

A7/A11
A8/A10
A3/A9
A10/A8
A11/A7
A2/A6
A1/A5
A0/A4
A9/A3
A6/A2
A5/A1
A4/A0

H3
G4
G9

RAS_N/BA2
BA0/BA1
BA1/BA0

15
15
15
15
15

IN
IN
IN
IN
IN

MC_CKE
MC_WE_N
MC_CAS_N
MC_RAS_N
MC_CS1_N

12

IN

MEM_SCAN_BOT_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

24
23

H9
H4
F9
H10
F4

MEM_C_VREF0
MEM_C_VREF1

IN
IN

H1
H12

V_MEM

IC
GDDR136
MF=1

MC_CLK1_DP

WE_N/CKE
CKE/WE_N
CS_N/CAS_N
BA2/RAS_N
CAS_N/CS_N

VREF1
VREF0

V_MEM

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

15
15
15
15
15
15
15
15

23
23
23
23
23
23
23
23
15
23 15
15

15
15
15
15
15
15
15
15

23
23
23
23
23
23
23
23
15
23 15
15

15
15
15
15
15
15
15
15

23
23
23
23
23
23
23
23
15
23 15
15

15
15
15
15
15
15
15
15

23
23
23
23
23
23
23
23
15
23 15
15

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

V_MEM
U3R1

1
2

C3T4
.1UF
10%
6.3V
X5R
402

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

IC
GDDR136
MF=1
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

C3T6

C2T3

X801995-011

MC_ZQ_BOT

1
1

R3R1

X801995-011

R3D3

2

549
1%
CH
402

2

MEM_C_VREF0

OUT

23

243
1%
CH
402

V_MEM
MEMORY C,

C2T1

.22UF
10%
6.3V
X5R
402

1

R3D2

2

1.27K
1%
CH
402

[PAGE_TITLE=MEMORY

C3D3
.1UF
10%
6.3V
X5R
402

PARITION

BOTTOM,

DECOUPLING

24

C,

TOP]

DRAWING
FALCON_FABD
Tue May 08 18:24:15

C3T1

.22UF
10%
6.3V
X5R
402

2007

C3T2
.22UF
10%
6.3V
X5R
402

C3T3
.22UF
10%
6.3V
X5R
402

C3T5
.22UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

C3T7
.22UF
10%
6.3V
X5R
402

.22UF
10%
6.3V
X5R
402

PROJECT NAME
FALCON_RETAIL

.22UF
10%
6.3V
X5R
402

PAGE
24/82

REV
1.0

CR-25

:

@FALCON_LIB.FALCON(SCH_1):PAGE25

MEMORY PARTITION

V_MEM

CHIP
1
60.4
1%
CH
402

2

R3E4

2

U3E1

IN

MD_CLK0_DN

13

IN
IN

MEM_RST
MD_A<11..0>

15

J11
J10

MD_BA<2..0>

IN

CLK_DP
CLK_DN

V9

RESET

11
10
9
8
7
6
5
4
3
2
1
0

L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4

A11/A7
A10/A8
A9/A3
A8/A10
A7/A11
A6/A2
A5/A1
A4/A0
A3/A9
A2/A6
A1/A5
A0/A4

2
1
0

H10
G9
G4

BA2/RAS_N
BA1/BA0
BA0/BA1

15
15
15
15
15

IN
IN
IN
IN
IN

MD_CKE
MD_WE_N
MD_CAS_N
MD_RAS_N
MD_CS0_N

H4
H9
F4
H3
F9

CKE/WE_N
WE_N/CKE
CAS_N/CS_N
RAS_N/BA2
CS_N/CAS_N

12

IN

MEM_SCAN_TOP_EN

A9

MF

IN

MEM_SCAN_EN

V4

SCAN_EN

12

25
26

MEM_D_VREF1
MEM_D_VREF0

IN
IN

H1
H12

VREF1
VREF0

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MD_DQ31
MD_DQ30
MD_DQ29
MD_DQ28
MD_DQ27
MD_DQ26
MD_DQ25
MD_DQ24
MD_WDQS3
MD_RDQS3
MD_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MD_DQ23
MD_DQ22
MD_DQ21
MD_DQ20
MD_DQ19
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_WDQS0
MD_RDQS0
MD_DM0

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

R2T4

2

549
1%
CH
402

15
15
15
15
15
15
15
15

26
26
26
26
26
26
26
26
15
26 15
15

15
15
15
15
15
15
15
15

26
26
26
26
26
26
26
26
15
26 15
15

15
15
15
15
15
15
15
15

26
26
26
26
26
26
26
26
15
26 15
15

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

1
2

C3R3
.1UF
10%
6.3V
X5R
402

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

X801995-011

MD_CS1_N

243
1%
CH
402

IN

15

V_MEM
MEMORY D,
PARTITION

OUT

25

26

1

1

2

C2T2
.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=MEMORY

PARTITION

C,

BOTTOM]

TOP,

DECOUPLING

D DECOUPLING
V_MEM
C2D2

MEM_D_VREF1

2

26
26
26
26
26
26
26
26
15
26 15
15

GDDR136
MF=0

R3E1

1

1.27K
1%
CH
402

15
15
15
15
15
15
15
15

IC

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

1
X801995-011

R2T3

U3E1
V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

MD_ZQ_TOP

V_MEM

2

V_MEM

V_MEM

IC
GDDR136
MF=0

15

15

TOP
= 0

MD_CLK0
STITCHING
CAP

60.4
1%
CH
402

MD_CLK0_DP

IN

D,

MIRROR FUNCTION

1

R3E5

15

SELECT = 0,

C2E2
4.7UF
10%
6.3V
X5R
805

.22UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:15

C2D1

.22UF
10%
6.3V
X5R
402

2007

C3D1
.22UF
10%
6.3V
X5R
402

C3D2
.22UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

C3D4
.22UF
10%
6.3V
X5R
402

C3D6
.22UF
10%
6.3V
X5R
402

C3D5
.22UF
10%
6.3V
X5R
402

PROJECT NAME
FALCON_RETAIL

C2D4
.22UF
10%
6.3V
X5R
402

PAGE
25/82

REV
1.0

CR-26

:

@FALCON_LIB.FALCON(SCH_1):PAGE26

MEMORY PARTITION
V_MEM

1

CHIP

60.4
1%
CH
402

15
13

2

IC
GDDR136
MF=1

15

IN

MD_CLK1_DN

IN
IN

MEM_RST
MD_A<11..0>

15

J11
J10

11
10
9
8
7
6
5
4
3
2
1
0

MD_BA<2..0>

IN

2
1
0

CLK_DP
CLK_DN

V9

RESET

L9
K11
M4
K2
L4
K3
H2
K4
M9
K10
H11
K9

A7/A11
A8/A10
A3/A9
A10/A8
A11/A7
A2/A6
A1/A5
A0/A4
A9/A3
A6/A2
A5/A1
A4/A0

H3
G4
G9

RAS_N/BA2
BA0/BA1
BA1/BA0

15
15
15
15
15

IN
IN
IN
IN
IN

MD_CKE
MD_WE_N
MD_CAS_N
MD_RAS_N
MD_CS1_N

12

IN

MEM_SCAN_BOT_EN

A9

MF

12

IN

MEM_SCAN_EN

V4

SCAN_EN

26
25

H9
H4
F9
H10
F4

MEM_D_VREF0
MEM_D_VREF1

IN
IN

= 1

60.4
1%
CH
402

MD_CLK1_DP

IN

BOTTOM

R2T6

U3T1
15

D,

MIRROR FUNCTION

1

R2T5

2

SELECT = 1,

H1
H12

WE_N/CKE
CKE/WE_N
CS_N/CAS_N
BA2/RAS_N
CAS_N/CS_N

VREF1
VREF0

V_MEM

V_MEM
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3

T3
T2
R3
R2
M3
N2
L3
M2
P2
P3
N3

MD_DQ23
MD_DQ22
MD_DQ21
MD_DQ20
MD_DQ19
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_DM2

BI
BI
BI
BI
BI
BI
BI
BI

DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2

T10
T11
R10
R11
M10
N11
L10
M11
P11
P10
N10

MD_DQ31
MD_DQ30
MD_DQ29
MD_DQ28
MD_DQ27
MD_DQ26
MD_DQ25
MD_DQ24
MD_WDQS3
MD_RDQS3
MD_DM3

BI
BI
BI
BI
BI
BI
BI
BI

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1

G10
F11
F10
E11
C10
C11
B10
B11
D11
D10
E10

MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_WDQS0
MD_RDQS0
MD_DM0

BI
BI
BI
BI
BI
BI
BI
BI

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0

G3
F2
F3
E2
C3
C2
B3
B2
D2
D3
E3

MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1

BI
BI
BI
BI
BI
BI
BI
BI

ZQ

A4

15
15
15
15
15
15
15
15

25
25
25
25
25
25
25
25
15
25 15
15

15
15
15
15
15
15
15
15

25
25
25
25
25
25
25
25
15
25 15
15

15
15
15
15
15
15
15
15

25
25
25
25
25
25
25
25
15
25 15
15

15
15
15
15
15
15
15
15

25
25
25
25
25
25
25
25
15
25 15
15

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

IN
OUT
IN

U3T1

V_MEM

1
2

IC

V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1

VDDQ<21>
VDDQ<20>
VDDQ<19>
VDDQ<18>
VDDQ<17>
VDDQ<16>
VDDQ<15>
VDDQ<14>
VDDQ<13>
VDDQ<12>
VDDQ<11>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
VDDQ<5>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDDQ<0>

V2
M12
M1
V11
F12
F1
A11
A2

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

K12
K1

VDDA<1>
VDDA<0>

J12
J1

VSSA<1>
VSSA<0>

GDDR136
MF=1
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>

T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1

VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

V3
L12
L1
G12
G1
A10
V10
A3

NC<1>
NC<0>

J3
J2

C2T7
4.7UF
10%
6.3V
X5R
805

X801995-011

MD_ZQ_BOT

1
1

R3T1

X801995-011

R3E3

2

549
1%
CH
402

2

MEM_D_VREF0

OUT

25

26

243
1%
CH
402

V_MEM
MEMORY D,

V_MEM
MEMORY D,

1

R3E2

2

1.27K
1%
CH
402

BOTTOM,

C2R7

C3R1

2007

MICROSOFT
CONFIDENTIAL

.22UF
10%
6.3V
X5R
402

DECOUPLING

BOTTOM,

.22UF
10%
6.3V
X5R
402

C3R2
.22UF
10%
6.3V
X5R
402

C3R4
.22UF
10%
6.3V
X5R
402

DECOUPLING

C3R7
.22UF
10%
6.3V
X5R
402

C3R6
.22UF
10%
6.3V
X5R
402

C2R10
.22UF
10%
6.3V
X5R
402

C2R8
.22UF
10%
6.3V
X5R
402

C3E4
.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=MEMORY

C2R13
.22UF
10%
6.3V
X5R
402

PARTITION

D,

BOTTOM]

C2T6
.22UF
10%
6.3V
X5R
402

C3E8
.22UF
10%
6.3V
X5R
402

C3F5
.22UF
10%
6.3V
X5R
402

C3U4
.22UF
10%
6.3V
X5R
402

C4F14
.22UF
10%
6.3V
X5R
402

C4F15
.22UF
10%
6.3V
X5R
402

C4U12
.22UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:15

PROJECT NAME
FALCON_RETAIL

PAGE
26/82

REV
1.0

CR-27

:

@FALCON_LIB.FALCON(SCH_1):PAGE27

HANA,

V_12P0

CLOCKS + STRAPPING

R4C11

1 R4B9

R3B2

1
1M
402

2

1%
CH

5%
CH

FT2P7

Y3B1
27MHZ

1

R4B1

1

2

22PF
5%
50V
NPO
402

1

1
2

C4B13

34

C3B6

FT4P1

22PF
5%
50V
NPO
402

1

1

FTP

HANA_POR_BYPASS

R4N5

2
1K
402

1
2

ANA_CLK_OE

IN

1

2

ANA_VRST_OK
ANA_V12P0_PWRGD
SMC_RST_N

68.1
402

34
34
34

R4C12
49
47

33
402

58

1
U4C2

1 OF 4

B6
M2
E12

R2P3

IC

E11
D10
M3

V_RST_OK
V_12P0_OK
SMC_RST_N*

V_12P0_DET
CORE_RST_N*
POR_BYPASS

1
1

2

1K
5%
CH
402

R2P1

P2
R2

XTAL_IN
XTAL_OUT

R4B17
5%
CH

1K
402

2

R3B1

10K
5%
EMPTY
402

HANA_XTAL_VSS_CAP

P3

XTAL_VSS_CAP

HANA_XTAL_BYPASS

M4

XTAL_BYPASS

N3

ANA_CLK_OE_R

R4P1

2
475
402

1

HANA_CLK_DRV_RSET2
HANA_CLK_DRV_RSET1

1%
CH

R4N6

475
402

58
58

K13
R11

CLK_DRV_RSET2
CLK_DRV_RSET1

34
34

BI
IN

SMB_DATA
SMB_CLK

HANA_TCLK
HANA_TDO
HANA_TDI
HANA_TMS
HANA_TRST

N1
P1

G12
F11
J12
F12
H12

GPU_CLK_DP_R

R10
P10

PCIEX_CLK_DP_R

SATA_CLK_DP
SATA_CLK_DN

R9
P9

SATA_CLK_DP_R

SATA_CLK_REF

R6

SATA_CLK_REF_R

M15
M14

ANA_PIX_CLK_2X_DP_R
ANA_PIX_CLK_2X_DN_R

1

ENET_CLK

P6

ENET_CLK_R

33
402

STBY_CLK

R8

STBY_CLK_R

AUD_CLK

R4

AUD_CLK_R

GPU_CLK_DP
GPU_CLK_DN

OUT
OUT

13
13

1%
CH

AV_CLK

N2

HANA_AV_CLK

R3C15 2

1

5%
CH

49.9
402

1%
CH

CPU_CLK_DN_R

R4C8

GPU_CLK_DN_R

33
402

R3C9

1

5%
CH

49.9
402

2

1%
CH

PCIEX_CLK_DP
PCIEX_CLK_DN

PCIEX_CLK_DN_R

R4B27 2

1

R3B5

1

OUT
OUT

2

1
1

SATA_CLK_DN_R

33
402

5%
CH

49.9
402

R4B26 2

R3B4

1
49.9
402

5%
CH

1%
CH

1

R4B25 2

2

1%
CH

33
402
FTP FT4N5

5%
CH

R4B6

1
33
402

R3B6

1
49.9
402

2

1
1

1%
CH

5%
CH

OUT
1

X802478-003

R4C15 2

2

5%
CH

33
402

2

1%
CH

49.9
402

R4C16 2

C3B1

10PF
5%
50V
EMPTY
402

5%
CH

33
402

49.9
402

13
13

OUT
OUT

R4C14 2

1

33

FTP FT2N4

ANA_PIX_CLK_2X_DP
ANA_PIX_CLK_2X_DN
1

J5C1

R4C13 2

1

1

33
33

FTP FT1P2
FTP FT1P1

SATA_CLK_REF

1
1

OUT
OUT

2

R4N4

10K
5%
CH
402

33
33

FTP FT3P2
FTP FT3P1

SATA_CLK_DP
SATA_CLK_DN
1

SMB_DATA
SMB_CLK

TCK <DN>
TDO
TDI
<UP>
TMS <UP>
TRST

49.9
402

R3C7

R13
P13

1%
CH

4
4

R3C16 2

1

5%
CH

5%
CH

NB_CLK_DP
NB_CLK_DN

PIX_CLK_OUT_DP
PIX_CLK_OUT_DN

OUT
OUT

1%
CH

1

CPU_CLK_DP_R

1

49.9
402

R3C8

R14
P14

ANA_CLK_OE

CPU_CLK_DP
CPU_CLK_DN

FTP FT2N3
FTP FT3P4

CPU_CLK_DP
CPU_CLK_DN

PCIEX_CLK_DP
PCIEX_CLK_DN

5%
EMPTY

1

2
1

1

2

1%
CH

R4C10 2

1

5%
CH

33
402

2

SMC_RST_N_R

49.9
402

FTP FT4P4

OUT
OUT
OUT

33
402

V_3P3STBY

34

1%
CH

10K
402

HANA_XTAL_IN

FTP

1 R4B2

HANA

HANA_XTAL_OUT

FT2P4

2
75
402

10K
402

ANA_RST_N

IN

1%
CH

470PF
5%
50V
EMPTY
402

HANA_V_12P0_DET

2

C3B7

R4B8

1

2

5%
CH

SM
XTAL

2

1

FTP

2
1K
402

R4C9

1

5%
CH

33
402

HANA_V_12P0_DET_R

1
1

1%
CH

FTP FT4P2
FTP FT4P3

2X3HDR
1
3
5

2
4
6

1
33
402

R4B5

2

ENET_CLK

5%
CH

SMB_CLK

STITCH

STBY_CLK

STITCH

SATA_CLK

STITCH
ENET_CLK

V_1P8STBY

1
2

V_1P8STBY

1

C2P7
.1UF
10%
6.3V
X5R
402

V_3P3STBY

2

C3N6

.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=HANA,

V_3P3

1
2

STITCH

SATA_CLK_REF

V_3P3

STITCH

33
402

10PF
5%
50V
EMPTY
402

.1UF
10%
6.3V
X5R
402

CLOCKS + STRAPING]

1
2

C1B4

.1UF
10%
6.3V
X5R
402

STBY_CLK

5%
CH

2

1
2

C2B14

.1UF
10%
6.3V
X5R
402

1
2

C2B17

R4B4

33
402

2

5%
CH

.1UF
10%
6.3V
X5R
402

2

DRAWING
FALCON_FABD
Tue May 08 18:24:16

2007

C3B2

10PF
5%
50V
EMPTY
402

AUD_CLK
1

34

OUT
1

V_3P3
1

C1P9

R4B24 2

40

C3B4

2
1

39

OUT
1

HDR

1

FTP FT2R2

1

FTP FT2P2

OUT

36

C3B12
10PF
5%
50V
EMPTY
402

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
27/82

REV
1.0

CR-28

:

@FALCON_LIB.FALCON(SCH_1):PAGE28

HANA,

VIDEO

U4C2
13

STBY_CLK

STITCH

V_1P8STBY

13

V_3P3STBY
1

1
2

C3P4

.1UF
10%
6.3V
X5R
402

1
2

C2R1

C2R2
.1UF
10%
6.3V
X5R
402

V_1P8STBY

2

1

.1UF
10%
6.3V
X5R
402

C3N10
.1UF
10%
6.3V
X5R
402

2

V_1P8STBY

14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

V_3P3STBY

1

C2P50
.1UF
10%
6.3V
X5R
402

2

V_3P3STBY
13
13

GPU_HSYNC_OUT
GPU_VSYNC_OUT

IN
IN

R4B12

2
787
402

R4B18 2

1

10K
402

29

10K
402

2

2

I2S_SD1

5%
CH

2

R4B15

10K
402

IN

SMC_PWM0

2
205K
402

R4C1

1

1%
CH

IN

1

PIX_DATA14
PIX_DATA13
PIX_DATA12
PIX_DATA11
PIX_DATA10
PIX_DATA9
PIX_DATA8
PIX_DATA7
PIX_DATA6
PIX_DATA5
PIX_DATA4
PIX_DATA3
PIX_DATA2
PIX_DATA1
PIX_DATA0

L14
L15

HSYNC_IN
VSYNC_IN

C8

HANA_DAC_RSET

1%
CH

M1

36
36

IN
IN

I2S_BCLK
I2S_WS

36

IN

I2S_SD

K1
K2
L2
K4
K3
L1

1

28

5%
CH

IN

GPU_TEMP_N

2

IN

EDRAM_TEMP_N

2

IN

FT4N4

FTP

A10
B10

VID_DACA_DP

OUT

44

B5
A5

VID_HSYNC_OUT_R
VID_VSYNC_OUT_R

OUT
OUT

44
44

TMDS_EXT_SWING
TMDS_TXC_DP
TMDS_TXC_DN

1
FT4N1

FTP

1

A2

TMDS_TX2_DP
TMDS_TX2_DN

H1
H2

TMDS_TX1_DP
TMDS_TX1_DN

F1
F2

TMDS_TX0_DP
TMDS_TX0_DN

D1
D2

SPDIF_OUT

B4

DDC_SCK
DDC_SDA

B3
A3

VID_DACB_DN

VID_DACA_DN

TEMP3_P
TEMP2_P
TEMP1_P
TEMP0_P
TEMPCAL_P

C13
B15
B13
A13
B14

BND_GAP_CAP
TEMP_RSET

V_3P3STBY

HDMI_EXT_SWING

422
402

1

1

44
34
34

2
44
44

29
29

HDMI_TXC_DN

OUT

29

HDMI_TX2_DP

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

301
603

C4B4

1 HDMI_TX2_DP_R

1

1%
CH

R4B19

2
301
603

.1UF 10%
6.3V
X5R
402

1

1%
CH

HDMI_TX1_DP
FAN1_OUT

2

OUT

C4B10

1

43

HDMI_TX1_DP_R

C4B11

1

HDMI_TX0_DP_R

V_1P8

HANA_OP2_OUT

1
0
402

R4B3

2

3

MMBT3906
XSTR
1

DB4P1
DB4P2
DB4P3
DB4P4

R4B21

1

1%
CH

2007

MICROSOFT
CONFIDENTIAL

OUT

28

CUSTOM THERMAL
CALIBRATION
PADS
LOCATION MUST
REMAIN LOCKED

CAL_TEMP_N
CPU_TEMP_P
GPU_TEMP_P
EDRAM_TEMP_P
BRD_TEMP_P

CAL_TEMP_P

DRAWING
FALCON_FABD
Tue May 08 18:24:16

HANA_OP2_DN

5%
CH

1
1

Q1G3

OUT

2

HDMI_TX0_DN

2

BRD_TEMP_P

1%
CH

301
603

.1UF 10%
6.3V
X5R
402

1
1

BRD_TEMP_N

1

HDMI_TX0_DP

.1UF
10%
6.3V
X5R
402

IN

R4B20

HDMI_TX1_DN

STITCH

C1P13

0.01UF
10%
16V
X7R
402

2
301
603

.1UF 10%
6.3V
X5R
402

C4B3

28

29

R4B22

2

.1UF 10%
6.3V
X5R
402

OUT
OUT
OUT

1%
CH

OUT

HDMI_TXC_DP_R

V_3P3

28

R4B14 2

1
37.4
402

HDMI_TXC_DP
C4B12

2

SATA_CLK_REF

+ FAN + JTAG]

1%
CH

2

HANA_SPDIF_OUT
HDMI_DDC_CLK
HDMI_DDC_DATA

2

1%
CH

R4B23 2

X802478-003

11K
1%
CH
402

R4B11

1
37.4
402

1%
CH

37.4
402

DB4P5

1

VIDEO

R4B13 2

1

SHORT

[PAGE_TITLE=HANA,

1%
CH

HDMI_TX2_DN

TEMP_N

A6

VID_DACC_DN

R4B10 2

1
37.4
402

B1
B2

A15

A14

VID_DACD_DN

1

2
2

1

2

DAC_A_OUT_DP
DAC_A_OUT_DN
HSYNC_OUT
VSYNC_OUT

ST4C3

CAL_TEMP_N

44

FAN1_FDBK

1

1

SHORT

IN

OUT

A12

2

ST4C4

28

VID_DACB_DP

FAN_OUT1

1

2

A9
B9

FAN_OUT2

1

SHORT

BRD_TEMP_N

DAC_B_OUT_DP
DAC_B_OUT_DN

FAN_OP1_DP
FAN_OP1_DN

1

ST4C5

IN

OUT

44

FAN_OP2_DP
FAN_OP2_DN

BND_GAP_CAP

SHORT

28

VID_DACC_DP

C12
B12

SHORT
ST4C2

13

A8
B8

HANA_OP2_DN

ST4C1

IN

DAC_C_OUT_DP
DAC_C_OUT_DN

I2S_SCK
I2S_WS
I2S_SD3
I2S_SD2
I2S_SD1
I2S_SD0

R4C2

13

44

SPDIF_IN

1

2

33

OUT

B11

.22UF
10%
6.3V
X5R
402

CPU_TEMP_N

OUT

VID_DACD_DP

HDMI_HPD

C4P2

IN

ANA_VID_INT

A7
B7

C11
A11

HANA_OP2_DP

TEMP_RSET

4

L3

DAC_D_OUT_DP
DAC_D_OUT_DN

DAC_RSET

A4

SB_SPDIF_OUT

FAN_OP1_DP

2

C14
C15
D14
D15
E14
E15
F14
F15
G15
H14
H15
J14
J15
K14
K15

IN

43

34

IC
VID_INT

I2S_SD2

36

10K
402

PIX_CLK_IN

HDMI_HPD

5%
CH

R4N2

1

G14

I2S_SD3

5%
CH

R4N3

1

1

2 OF 4
HANA

GPU_PIX_CLK_1X
PIX_DATA<14..0>

IN
IN

+ FAN + JTAG

OUT
OUT
OUT
OUT
OUT

PROJECT NAME
FALCON_RETAIL

28
4
13
13
28

PAGE
28/82

REV
1.0

CR-29

:

@FALCON_LIB.FALCON(SCH_1):PAGE29

R2A11
5%
CH
44

NA
SM

1

CM2A1 EMPTY
28

IN

HDMI_TX2_DP

1

CMCHOKE

1
4

3

ESDB-MLP7
402

X801560-001

R2A12
5%
CH

EG2A1

DIO

DIO

.1UF
10%
6.3V
X5R
402

FTP FT3M1
FTP FT3M2

1

J2A1

FTP FT3M3

1

FTP FT3M4

HDMI_TX2_DP_CM

2

HDMI_TX2_DN_CM

2

0
603

EG2A2

C2A9

2

FTP FT2M5

1

ESDB-MLP7
402

1

HDMI_TX2_DN

1

IN

1

FTP FT2M4

1
28

V_AVIP

FTP FT2M3

1

2

IN

FTP FT2M2

1

HDMI_TX1_DP_CM
HDMI_TX1_DN_CM
HDMI_TX0_DP_CM

R2A13
HDMI_TX0_DN_CM

5%
CH

HDMI_TXC_DP_CM

NA
SM

HDMI_TXC_DN_CM

CM2A2 EMPTY

4

1

3

X801560-001

R2A14
5%
CH

ESDB-MLP7
402

ESDB-MLP7
402

EG2A4

EG2A3

DIO

DIO

2

0
603

1

R3M5

2
34 28
28 44
34
44

IN
IN

R3M6

2K
1%
CH
402

2

5%
CH

1

BAV99
DIO

4
ESDB-MLP7
402

EG3M2

1

R3M1
BAV99
DIO

ESDB-MLP7
402

X801560-001

5%
CH

EG3A1

DIO

DIO

2

0
603

EG3A2

HDMI_HPD

OUT

28

2
EMPTY

PGB0010603
603

EG3M1

47K
5%
CH
402

DIO

2

R3A11

ESDB-MLP7
402

2

5%
CH

2

3

ESDB-MLP7
402

EG3M3

EMPTY
4

R3M7

10K
402
3

1
2

X806395-002

2

HDMI_TX0_DN

CMCHOKE

ME4
ME3
ME2
ME1

5
6

1

IN

1

FTP FT2N6

23
22
21
20

1

1

1

28

HDMI_TX0_DP

FTP FT4N2

CR3M1

2

NA
SM
IN

1

CR3M1

CM3A1 EMPTY
28

2K
1%
CH
402

HDMI_DDC_CLK
HDMI_DDC_DATA

R3A10
0
603

HDMI_CEC

HDMI
TMDS_DATA2_DP
TMDS_DATA2_SHD
TMDS_DATA2_DN
TMDS_DATA1_DP
TMDS_DATA1_SHD
TMDS_DATA1_DN
TMDS_DATA0_DP
TMDS_DATA0_SHD
TMDS_DATA0_DN
TMDS_CLK_DP
TMDS_CLK_SHD
TMDS_CLK_DN
CEC
RESERVED
SCL
SDA
DDC_CEC_GND
5VCC
HOT_PLUG_DET

1

HDMI_TX1_DN

1

2

1

IN

CMCHOKE

1

IN

1

2

28

HDMI_TX1_DP

1

28

DB3A1

V_5P0STBY

HDMI_HPD_PIN

0
603

HDR

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

2

0
603

R3A12
0
603

5%
CH

NA
SM
CM3A2 EMPTY
1

28

IN

HDMI_TXC_DN

4

CMCHOKE

2

3

X801560-001

[PAGE_TITLE=CONN,

HDMI]

5%
CH

2

R3A13
0
603

ESDB-MLP7
402

1

HDMI_TXC_DP

ESDB-MLP7
402

EG3A4

EG3A3

DIO

DIO

2

IN

1

28

DRAWING
FALCON_FABD
Tue May 08 18:24:16

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
29/82

REV
1.0

CR-30

:

@FALCON_LIB.FALCON(SCH_1):PAGE30

HANA,

POWER + DECOUPLING

V_3P3STBY
FB4N5
1

2

120
0.2A
C4N360.5 DCR
4.7UF
10%
6.3V
X5R
805

V_HANA_VAA_RTS33S

FB
603

1

C4N37
4.7UF
10%
6.3V
X5R
805

2

C4N35
.1UF
10%
6.3V
X5R
402

V_1P8STBY
U4C2

IC

3 OF 4
HANA

V_3P3

D12
D11

FB4N8
1

C4N15

60
0.5A
0.1DCR

2

V_HANA_VAA_DAC33M

FB
603

1

4.7UF
10%
6.3V
X5R
805

2

C4N24

C4N23

4.7UF
10%
6.3V
X5R
805

.1UF
10%
6.3V
X5R
402

1
2

C4N29
.1UF
10%
6.3V
X5R
402

V_3P3STBY

V_3P3STBY
R4N1

1
100
402

2

V_HANA_VAA_XTAL_33S

5%
CH

1

C4N16
.1UF
10%
6.3V
X5R
402

2

VAA_DAC33M3
VAA_DAC33M2
VAA_DAC33M1
AVSS_DAC33M1

C7
D7

VAA_DAC33M0
AVSS_DAC33M0

C6

VAA_POR33S

C10

VAA_FAN33S

R3

VAA_XTAL33S

N8
P8

VDDIO33S_STBY_PLL
VSSIO33S_STBY_PLL

M6
N6

VDDIO33S_25M_PLL
VSSIO33S_25M_PLL

P5
R5

2

C4N25
4.7UF
10%
6.3V
X5R
805

1
2

C4N8
4.7UF
10%
6.3V
X5R
805

VAA_GP_PLL
AVSS_GP_PLL

M12
M13
R7
P7

VAA_100M_PLL_A
AVSS_100M_PLL_A1
AVSS_100M_PLL_A0

N15
P15
R15

VAA_100M_PLL_D
AVSS_100M_PLL_D

R12
P12

VDDC_STBY_PLL
VSSC_STBY_PLL

N7
M7

VDDC_25M_PLL
VSSC_25M_PLL

N5
M5

VDDC_AUD_PLL
VSSC_AUD_PLL

N4
P4

VDD_DAC18S
VAA_POR18S

E7
D6

1

VDDIO18S_100M_PLL5
VDDIO18S_100M_PLL4
VDDIO18S_100M_PLL3

N14
N13
P11

2

VDDIO18S_100M_PLL2
VSSIO18S_100M_PLL2

M10
N12

VDDIO18S_100M_PLL1
VSSIO18S_100M_PLL1

N9
N11

VDDIO18S_100M_PLL0
VSSIO18S_100M_PLL0

M9
N10

VDDIO18S_PIX_PLL
VSSIO18S_PIX_PLL

L13
L12

VDDIO33S_AUD_PLL
VSSIO33S_AUD_PLL

V_3P3STBY

1

VAA_VID_PLL
AVSS_VID_PLL

VAA_RTS33S
AVSS_RTS33S

E9
D9
C9
D8

V_1P8STBY

1

C3C6
4.7UF
10%
6.3V
X5R
805

2

C4P13
4.7UF
10%
6.3V
X5R
805

1
2

C3N3
4.7UF
10%
6.3V
X5R
805

X802478-003

V_1P8STBY
V_3P3STBY

1
1
2

C4N18

.1UF
10%
6.3V
X5R
402

1
2

C4N19

.1UF
10%
6.3V
X5R
402

[PAGE_TITLE=HANA,

1
2

C4N20
.1UF
10%
6.3V
X5R
402

1
2

C4N28
.1UF
10%
6.3V
X5R
402

1
2

C4P8

.1UF
10%
6.3V
X5R
402

1
2

C4N42

.1UF
10%
6.3V
X5R
402

POWER + DECOUPLING]

2

C4N31
.1UF
10%
6.3V
X5R
402

1
2

C4N17
.1UF
10%
6.3V
X5R
402

1
2

C4P5
.1UF
10%
6.3V
X5R
402

1
2

C4N34
.1UF
10%
6.3V
X5R
402

1
2

C4P6

.1UF
10%
6.3V
X5R
402

1
2

C4N27

.1UF
10%
6.3V
X5R
402

1
2

C4P11
.1UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:16

1
2

C4P1
.1UF
10%
6.3V
X5R
402

2007

1
2

C4P9
.1UF
10%
6.3V
X5R
402

1
2

C4N26
.1UF
10%
6.3V
X5R
402

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
30/82

REV
1.0

CR-31

:

@FALCON_LIB.FALCON(SCH_1):PAGE31

HANA,

POWER + DECOUPLING

V_3P3STBY
U4C2

4 of

4

IC

V_1P8STBY

HANA
E13
J4
J3
C3

V_3P3STBY
FB4N6
1

C4N3

120
0.5A
0.2DCR

4.7UF
10%
6.3V
X5R
805

V_HANA_VDDIO_33S_AVCC

2
FB
603

1
2

C4N6

4.7UF
10%
6.3V
X5R
805

1

C4N9
.1UF
10%
6.3V
X5R
402

2

1

C4N10
.1UF
10%
6.3V
X5R
402

C4N14
.1UF
10%
6.3V
X5R
402

2

1
2

C4N13

.1UF
10%
6.3V
X5R
402

V_3P3STBY

1

C4N5

2

F4
E4
F3
G4
G3
C2
G1
C1
G2

VSSIO_33S_AVSS8
VSSIO_33S_AVSS7
VSSIO_33S_AVSS6
VDDIO_33S_AVCC5
VDDIO_33S_AVCC4
VDDIO_33S_AVCC3
VDDIO_33S_AVCC2
VDDIO_33S_AVCC1
VDDIO_33S_AVCC0

A1
E1
J1
E2
E3
J2

VSSIO_33S_AVSS5
VSSIO_33S_AVSS4
VSSIO_33S_AVSS3
VSSIO_33S_AVSS2
VSSIO_33S_AVSS1
VSSIO_33S_AVSS0

H3

VDDIO_33S_PVDD1

D3

VDDIO_33S_PVCC0

H4
D4

VSSIO_33S_PVSS1
VSSIO_33S_PVSS0

C4N12

.1UF
10%
6.3V
X5R
402

.1UF
10%
6.3V
X5R
402

VDD33S3
VDD33S2
VDD33S1
VDD33S0

V_3P3STBY
FB4N7
1

C4N4

4.7UF
10%
6.3V
X5R
805

120
0.2A
0.5
DCR

V_HANA_VDDIO_33S_PVCC0

2
FB
603

1
2

C4N7

4.7UF
10%
6.3V
X5R
805

C4N11
.1UF
10%
6.3V
X5R
402

FB4P1
VDD18S21
VDD18S20
VDD18S19
VDD18S18
VDD18S17
VDD18S16
VDD18S15
VDD18S14
VDD18S13
VDD18S12
VDD18S11
VDD18S10
VDD18S9
VDD18S8
VDD18S7
VDD18S6
VDD18S5
VDD18S4
VDD18S3
VDD18S2
VDD18S1
VDD18S0
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

L11
K11
G11
J10
H10
J9
H9
M8
L8
K8
G8
F8
L7
K7
G7
F7
J6
H6
J5
H5
E5
D5

1

V_HANA_VDD18S

1
2

1
2

C4N32

.1UF
10%
6.3V
X5R
402

C4P4

.1UF
10%
6.3V
X5R
402

1
2

C4N30

.1UF
10%
6.3V
X5R
402

1

120
0.5A
0.2DCR

C4P3

2
FB
603

1

4.7UF
10%
6.3V
X5R
805

2

1
2

2

C4N41
.1UF
10%
6.3V
X5R
402

1
2

C4N33

.1UF
10%
6.3V
X5R
402

1
2

C4N22
.1UF
10%
6.3V
X5R
402

C3P1
4.7UF
10%
6.3V
X5R
805

1
2

C4P7
.1UF
10%
6.3V
X5R
402

1
2

C4N21

.1UF
10%
6.3V
X5R
402

J13
H13
G13
F13
D13
K12
M11
J11
H11
L10
K10
G10
F10
E10
L9
K9
G9
F9
J8
H8
E8
J7
H7
L6
K6
G6
F6
E6
L5
K5
G5
F5
C5
L4
C4
R1

X802478-003

[PAGE_TITLE=HANA,

POWER + DECOUPLING]

DRAWING
FALCON_FABD
Tue May 08 18:24:16

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
31/82

REV
1.0

CR-32

:

@FALCON_LIB.FALCON(SCH_1):PAGE32

POWER TRACE DECOUPLING
V_12P0

V_12P0

1

C7G2

2

1

10%
0.01UF
16V
X7R
402

1

C4N40

C9F2

C3N2

2

0.01UF
10%
16V
X7R
402

2

1

C1N12

2

10%
0.01UF
16V
X7R
402

0.01UF
10%
16V
X7R
402

1

V_5P0STBY

2

1

0.01UF
10%
16V
X7R
402

C1C7

2

0.01UF
10%
16V
X7R
402

V_3P3STBY

1

C7B1

2

.1UF 10%
6.3V
X5R
402

1

C6B1

2

.1UF 10%
6.3V
X5R
402

1

C4A1

2

.1UF 10%
6.3V
X5R
402

V_5P0DUAL

1

C2F2

2

1

.1UF 10%
6.3V
X5R
402

1

C2G1

C3G3

C1C8

2

.1UF 10%
6.3V
X5R
402

2

1

.1UF 10%
6.3V
X5R
402

1

55

C8G2

2

.1UF 10%
6.3V
X5R
402

2

1

.1UF 10%
6.3V
X5R
402

C1F1

IN

V_VREG_V1P8V5P0

1

C4F13

2

0.01UF
10%
16V
X7R
402

1

C5G1

2

0.01UF
10%
16V
X7R
402

2

.1UF 10%
6.3V
X5R
402

V_5P0
1

C9E2

2

1

0.01UF
10%
16V
X7R
402
1
1

C9C7

2

0.01UF
10%
16V
X7R
402

1

2

0.01UF
10%
16V
X7R
402

C7N1

2

0.01UF
10%
16V
X7R
402

C2T4

1

C5G3

2

1

.1UF 10%
6.3V
X5R
402

C1B2

2

1

C1C12

.1UF 10%
6.3V
X5R
402

.1UF 10%
6.3V
X5R
402

C1C1

C1N13

1
1

2

.1UF 10%
6.3V
X5R
402

1

2

.1UF 10%
6.3V
X5R
402

1
1

C1D10

2

.1UF 10%
6.3V
X5R
402

1

C1G1

2

.1UF 10%
6.3V
X5R
402

C6N1

2

1

0.01UF
10%
16V
X7R
402

C1B3

2

.1UF 10%
6.3V
X5R
402

1

C1F2

2

.1UF 10%
6.3V
X5R
402

1

C4N1

C5N2

2

C3N1

2

.1UF 10%
6.3V
X5R
402
C7N2

2

.1UF 10%
6.3V
X5R
402

2

0.01UF
10%
16V
X7R
402

1

2

.1UF 10%
6.3V
X5R
402

1

C5N1

C9N1

.1UF 10%
6.3V
X5R
402

1
1

2

2

2

.1UF 10%
6.3V
X5R
402

C5G5

.1UF 10%
6.3V
X5R
402

V_1P8
1

2

.1UF 10%
6.3V
X5R
402

1
1

C3U3

2

2

.1UF 10%
6.3V
X5R
402

1

C1C15

C5V1

C1D8

.1UF 10%
6.3V
X5R
402

2

0.01UF
10%
16V
X7R
402

[PAGE_TITLE=POWER

TRACE EMI

CAPS]

DRAWING
FALCON_FABD
Tue May 08 18:24:16

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
32/82

REV
1.0

CR-33

:

@FALCON_LIB.FALCON(SCH_1):PAGE33

ADB:ADD

CONFIG

SB,

TABLE

PCIEX

+ SMM GPIO
U2C1

+ JTAG]
1 of

SB VERSION

R2P9

2
1K
402

V_3P3

1

5%
CH

27
27

IN
IN

27

IN

DB1N5

R2P5

2

V_1P8
R2P16

2
1K
402

1K
402

1

5%
EMPTY

1

TP

1

5%
EMPTY

DB2P15
TP

R2P2

1K
402

13
13
13
13

TP

1

5%
EMPTY

K1
J1

SATA_CLK_DP
SATA_CLK_DN

SATA_CLK_REF

H3

SATA_CLK_REF

SATA_CLK_SEL

H4

SATA_CLK_SEL<UP>

ECB_CLK_BYP
ECB_CLK_SEL

A6
B6

ECB_CLK_BYP<DN>
ECB_CLK_SEL<DN>

HBEDB_CLK_BYP
HBEDB_CLK_SEL

U20
V20

HBEDB_CLK_BYP<DN>
HBEDB_CLK_SEL<DN>

1

XUSB_CLK_BYP
XUSB_CLK_SEL

B15
C15

XUSB_CLK_BYP<DN>
XUSB_CLK_SEL<DN>

L22
L21

PEX_CLK_DP
PEX_CLK_DN

IN
IN

PCIEX_CLK_DN
27
IN
PCIEX_CLK_DP
27
IN
PEX_GPU_SB_L1_DP
PEX_GPU_SB_L1_DN

P22
N22

PEX_RX1_DP
PEX_RX1_DN

IN
IN

PEX_GPU_SB_L0_DP
PEX_GPU_SB_L0_DN

T21
R21

PEX_RX0_DP
PEX_RX0_DN

K20
K19

PEX_RBIAS1
PEX_RBIAS0

D15

UART0_RXD<UP>

PEX_RBIAS1
PEX_RBIAS0

1

1
2

R2P11

C2P25
.1UF
10%
6.3V
X5R
402

1

124
1%
CH
402

2

2

58

1

IN

KER_DBG_RXD

R2P8

C2P18
.1UF
10%
6.3V
X5R
402

2

499
1%
CH
402

V_3P3

1

1

R1P6

2

10K
5%
EMPTY
402

2

0

1

2

GPIO<1>

2

2

1

R1C6

2

10K
5%
EMPTY
402

1K
5%
EMPTY
402

2

10K
5%
EMPTY
402

2

1

R2B10

2

10K
5%
EMPTY
402

1K
5%
CH
402

R2N5

2

14

1
1K
5%
CH
402

1

R2N4

11

R1C2

2

1

R2N6

5

1
1K
5%
EMPTY
402

1

R1P1

10K
5%
CH
402
3

R1C5

1K
5%
CH
402

1

R1P5

2

1

R1C4

2

10K
5%
CH
402
2

1
1K
5%
CH
402

1

R1P3

10K
5%
EMPTY
402
1

R1C7

2

1

R1P2

SB_GPIO<0..15>

BI

33

1

R2B8

2

10K
5%
EMPTY
402
15

1K
5%
CH
402

R2B9

2

1K
5%
CH
402

SB_TCLK
SB_TDO
SB_TDI
SB_TMS
SB_TRST

= 0 ENABLE DEBUG OUTPUT
1 DISABLE
DEBUG OUTPUT

W20
V22
V21
W22
W21

IC
106

C2C2

1

TCK<DN>
TDO
TDI<UP>
TMS<UP>
TRST<DN>

2

PEX_SB_GPU_L1_DP

OUT

13

58

PEX_SB_GPU_L1_DN

OUT

13

58

PEX_SB_GPU_L0_DP

OUT

13

58

PEX_SB_GPU_L0_DN

OUT

13

58

.1UF 10%
6.3V
X5R
402
C2C1

1

1

DB2N8

2

SATA_CLK_DP
SATA_CLK_DN

6

2

.1UF 10%
6.3V
X5R
402
C2C4

1

2

.1UF 10%
6.3V
X5R
402
PEX_TX1_DP
PEX_TX1_DN

N20
M20

PEX_SB_GPU_L1_DP_C

PEX_TX0_DP
PEX_TX0_DN

R19
P19

PEX_SB_GPU_L0_DP_C

UART0_TXD

D14

KER_DBG_TXD_R

GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0

D10
D11
D12
D13
C8
D9
C9
B9
A9
C10
B10
A10
C11
B11
A11
C12
B12
A12
C13
B13
A13
C14
B14
A14
E3
F1
F2
F3
G1
G2
G3
G4

C2C3

1

2

PEX_SB_GPU_L1_DN_C

.1UF 10%
6.3V
X5R
402

PEX_SB_GPU_L0_DN_C

R2N8

2
47
402

SB_GPIO_RESERVED31
SB_GPIO_RESERVED30
SB_GPIO_RESERVED29
SB_GPIO_RESERVED28
SB_GPIO_RESERVED27
SB_GPIO_RESERVED26
SB_GPIO_RESERVED25
SB_GPIO_RESERVED24
SB_GPIO_RESERVED23
SB_GPIO_RESERVED22
SB_GPIO_RESERVED21
SB_GPIO_RESERVED20
SB_GPIO_RESERVED19
SB_GPIO_RESERVED18
SB_GPIO_RESERVED17
SB_GPIO_RESERVED16

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

SCART_RGB
AUD_RST_N

KER_DBG_TXD

DB2P1
DB2P2
DB2P3
DB2P4
DB2P5
DB2P6
DB2P7
DB2N6
DB2N5
DB2N4
DB2N3
DB2N11
DB2N12
DB2N10
DB2N9
DB2N7

15
14

OUT

58

SB_GPIO<0..15>

BI

33

44
41

OUT
OUT
ANA_VID_INT
IN
WSS_CNTL0
OUT
WSS_CNTL1
OUT
PCIEX_INT
SB_GPIO_RESERVED6

11
28
44
44

DB1P1
TP

DB1P2

1

TP

1
5

ENET_RST_N

OUT

1
SATA_CLK

1

5%
CH

V_3P3

39

40

3
2
1
0

FTP FT1N1

STITCH

V_3P3

J2D1
GPIO<0,2,3>

=

111
110
101
100
011
010

[PAGE_TITLE=SB,

XENON
ZEPHYR
ZEPHYR
ZEPHYR
FALCON
JASPER

X02047-012

2X3HDR
A
B
C

1
3
5

2
4
6

1

HDR

PCIEX

+ SMM GPIO

2

+ JTAG]

C1C2

.1UF
10%
6.3V
X5R
402

2
1

C2B16
.1UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:16

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
33/82

REV
1.0

CR-34

:

@FALCON_LIB.FALCON(SCH_1):PAGE34

SB,
V_3P3STBY

27
27

SMC
V_12P0

STBY_CLK
SMC_RST_N

IN
IN

2

R8N17
4.7K
5%
CH
402

C2P51
48

OUT

1UF
10%
16V
X7R
603

R2N15 1

2

TRAY_OPEN

33
402

5%
CH

1

VREG_GPU_PWRGD
58

29

44

44

28

10K
402

58

1
U2C1

5%
CH

FTP

1

1

1

R2P6

FT2P24
FT2P15
58
27

FTP
FTP

1
1

2

BI
BI

SMB_DATA
SMB_CLK

IN

AV_MODE2

44

IN

AV_MODE1

2

44

IN

AV_MODE0

2

27
58

C17

SMC_RST_N*

G20

SB_RST_N*

34

IN

SB_MAIN_PWRGD

G19

MAIN_PWR_OK

D16

SMC_UART1_RXD<UP>

58

IN

SMC_DBG_EN

C16

SMC_DBG<DN>

FTP

29

44

28

2

2.2K
5%
CH
402

2

TRAY_OPEN_R

48
41

IN

TRAY_STATUS

OUT

AUD_CLAMP

EXT_PWR_ON_R

R2M3

1

AV_MODE1_R
AV_MODE0_R

10K
402

10K
402

10K
402

5%
CH

R2M5

1

5%
CH

R2A2

TP
DB2P8

GPU_TCLK_R
ANA_VRST_OK
VREG_V5P0_VMEM_PWRGD

TP
DB2P9

BI

IR_DATA

IN

58

B16

SMC_UART1_TXD

SMC_DBG_TXD_R

2

10K
402

5%
CH

E22
E21
E20
E19
F22
F21
F20
F19

PWRSW_N
VREG_3P3_EN
ANA_V12P0_PWRGD

OUT
IN

27

ANA_RST_N
VREG_GPU_EN_N
PSU_V12P0_EN
ANA_CLK_OE

OUT
OUT
OUT
OUT

27
53
49
27

B20
B21
C20
C22
C21
D22
D21
D20

SMC_P3_GPIO7
SMC_P3_GPIO6
SMC_P3_GPIO5
SMC_P3_GPIO4
SMC_P3_GPIO3
SMC_P3_GPIO2
SMC_P3_GPIO1
SMC_P3_GPIO0

SMC_P1_GPIO7
SMC_P1_GPIO6
SMC_P1_GPIO5
SMC_P1_GPIO4
SMC_P1_GPIO3
SMC_P1_GPIO2
SMC_P1_GPIO1
SMC_P1_GPIO0

Y21
Y22
AA20
AA21
AB20
Y20
AA19
AB19

VREG_CPU_EN

OUT

51

VREG_V5P0_EN
VREG_V5P0_SEL
VREG_V1P8_EN
BINDSW_N
TILTSW_N
EJECTSW_N

OUT
OUT
OUT
IN
IN
IN

55
47
55
43
43
43

SMC_P0_GPIO7
SMC_P0_GPIO6
SMC_P0_GPIO5
SMC_P0_GPIO4
SMC_P0_GPIO3
SMC_P0_GPIO2
SMC_P0_GPIO1
SMC_P0_GPIO0

J20
H21
H19
H20
J19
J22
J21
H22

GPU_RST_DONE_R

OUT

4

2

OUT

34

1K
402

A17
B17

SMC_PWM1 1
SMC_PWM0

G22
G21

SMC_PWM1
SMC_PWM0

SMC_IR_IN

OUT

1K
402

13
4 60

OUT

28

FTP

FT2P25
FT1U2

FTP
FTP

R2P15

10K
5%
CH
402

1

FTP FT2P5

SB_MAIN_PWRGD

5%
CH

34

OUT

10K
5%
CH
402

1

V_1P8STBY

1

1

R2P12

U1U1

2
2K
1%
CH
402

DBG_LED0
DBG_LED0

SMC]

13

ENTEST1_N*<UP>
ENTEST0_N*<UP>

1
1

R2B16

[PAGE_TITLE=SB,

IN

R2P10

1

1

N:

GPU_RST_DONE
2

1

V_5P0DUAL

2

1

5%
CH

1

DBG_LED0

V_3P3STBY

51

IN

R3P6

X02047-012
FT3P3

R3P7

2

1

OUT
OUT
DB2B1

5%
CH

49
56

2

GPU_RST_N
CPU_PWRGD

V_5P0

2

VREG_CPU_PWRGD

SMC_P2_GPIO7
SMC_P2_GPIO6
SMC_P2_GPIO5
SMC_P2_GPIO4
SMC_P2_GPIO3
SMC_P2_GPIO2
SMC_P2_GPIO1
SMC_P2_GPIO0

CPU_RST_N
SB_MAIN_PWRGD_R
SB_RST_N

R7V4

1

R2N9

1

53

1%
CH

1.82K
402

SMC_P4_GPIO7
SMC_P4_GPIO6
SMC_P4_GPIO5
SMC_P4_GPIO4
SMC_P4_GPIO3
SMC_P4_GPIO2
SMC_P4_GPIO1
SMC_P4_GPIO0

A16

EN_TEST1_N
EN_TEST0_N

1
1

OUT

A18
B18
C18
D18
A19
B19
C19
A20

1

DB1F1
34

106

47
402

5%
CH

43

BI
BI
BI

SMC_DBG_TXD

IN

R8N18 2

1

IC

N: TIED TO V_MEMPORT
FOR BETTER ROUTING

HDMI_DDC_CLK

OUT

13
27
55

6

R2P4

2.2K
5%
CH
402

AV_MODE2_R

44

STBY_CLK

SB_RST_N

34

V_3P3STBY

1

Y12

IN

FT2P10

SMC_CPU_CHKSTOP_DETECT

BI

2 of

SB VERSION

HDMI_DDC_DATA

BI

FT2N5

R2N21

2

EXT_PWR_ON_N

IN

2

SN74LVC1G14

R2B19

1

V_5P0DUAL

IC

2K
1%
EMPTY
402

34

IN

DBG_LED0

5
2
3

VCC
IN
GND

OUT
N/C

4
1

DBG_LED0_LED_R

1
249
402

2

R1U3
1%
CH

DBG_LED0_LED

2
LED

10K
5%
CH
402

R2P13

2

10K
5%
CH
402

D1F1

ARGON_DATA
ARGON_CLK

1

YELLOW
SM

BI
BI

49
49

X801189-001

PULLDOWN = SMC PRODUCTION MODE
PULLUP
= SMC DEVELOPMENT MODE

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
34/82

REV
1.0

CR-35

:

@FALCON_LIB.FALCON(SCH_1):PAGE35

SB,

FLASH
U2C1

58
58
58

42
42

SPI_CLK
SPI_MOSI
SPI_SS_N

IN
IN
IN

FLSH_DATA<7..0>

BI

7
6
5
4
3
2
1
0

FLSH_WP_N

OUT
V_3P3STBY
2

42

IN

2.2K
402

FLSH_READY

FTP
FTP

FT2P22
FT2P23
FT2P20
FT2P21

FTP
FTP
46
46
46
46

R1P7

1

5%
CH

1
1

USBPORTA3_DP
USBPORTA3_DN

1
1

USBPORTA2_DP
USBPORTA2_DN

SPI_CLK
SPI_MOSI
SPI_SS_N*<UP>

Y2
AA2
Y3
AA3
AB3
Y4
AA4
AB4

FLSH_DATA7
FLSH_DATA6
FLSH_DATA5
FLSH_DATA4
FLSH_DATA3
FLSH_DATA2
FLSH_DATA1
FLSH_DATA0

W18
Y18
AA17
AB17

IC
106
SPI_MISO

AB5

2

SPI_MISO_R

R1R1

33
402

1

SPI_MISO

W1

FLSH_CLE

OUT

42

FLSH_CE_N*

V3

FLSH_CE_N

OUT

42

FLSH_RE_N*

V2

FLSH_RE_N

OUT

42

FLSH_WE_N*

W3

FLSH_WE_N

OUT

42

FLSH_ALE

W2

FLSH_ALE

OUT

42

FLSH_CLE

FLSH_WP_N*<DN>
FLSH_READY

USBA_D3_DP
USBA_D3_DN

USBB_D4_DP
USBB_D4_DN

Y10
W10

ARGONPORT_DP
ARGONPORT_DN

BI
BI

49
49

USBA_D2_DP
USBA_D2_DN

USBB_D3_DP
USBB_D3_DN

Y8
W8

MEMPORT1_DP
MEMPORT1_DN

BI
BI

46
46

W16
Y16

USBA_D1_DP
USBA_D1_DN

USBB_D2_DP
USBB_D2_DN

AB7
AA7

EXPPORT_DP
EXPPORT_DN

BI
BI

45
45

BI
BI

GAMEPORT1_DP
GAMEPORT1_DN

AA15
AB15

USBA_D0_DP
USBA_D0_DN

USBB_D1_DP
USBB_D1_DN

AB9
AA9

MEMPORT2_DP
MEMPORT2_DN

BI
BI

46
46

USB_RBIAS

USBB_D0_DP
USBB_D0_DN

AB11
AA11

MEMPORT3_DP
MEMPORT3_DN

BI
BI

60
60

SB_USB_RBIAS

2

OUT

5%
CH

GAMEPORT2_DP
GAMEPORT2_DN

1

FLASH

6

BI
BI

W12

[PAGE_TITLE=SB,

3 of
SB VERSION

U3
Y5
AA5

Y1
V1

+ USB + SPI

58

X02047-012

1

R2P14

C2P40
.1UF
10%
6.3V
EMPTY
402

+ USB + SPI]

2

113
1%
CH
402

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
35/82

REV
1.0

CR-36

:

@FALCON_LIB.FALCON(SCH_1):PAGE36

SB,

40

39

IN

MII_TX_CLK

IN

MII_RX_CLK

R1B9

39

+ SATA

MII_TX_CLK_R

R1B10
33
402

40

+ AUDIO

5%
CH

33
402

U2C1
40

ETHERNET

MII_RX_CLK_R

5%
CH

B3
C3

MII_TX_CLK
MII_RX_CLK

IN
IN
IN
IN

MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0

D1
D2
D3
C1

MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0

39
39

IN
IN

MII_RXDV
MII_RXER

C2
B2

MII_RXDV
MII_RXER

40 39
40 39
39

IN
IN
BI

MII_COL
MII_CRS
MII_MDIO

B5
A5
E1

MII_COL
MII_CRS
MII_MDIO

40
40
40
40

39
39
39
39

40
40

27

4 of

6

SB VERSION

MII_MDC_CLK_OUT

R1C3

MII_MDC_CLK_OUT_R

IC

MII_MDC_CLK_OUT

AUD_CLK

A8

AUD_CLK

C5
A4
B4
C4

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

MII_TXEN

A3

MII_TXEN

OUT
OUT
OUT
OUT
OUT

39
39
39
39

40
40
40
40
39

40

R2B11

I2S_MCLK_OUT
I2S_BCLK_OUT
I2S_SD
I2S_WS
SPDIF

C7
B8
A7
B7
C6

I2S_SD_R
SPDIF_R

47
402

SATA1_RX_DP
SATA1_RX_DN

SATA1_TX_DP
SATA1_TX_DN

R2
P2

HDD_TX_DP
HDD_TX_DN

OUT
OUT

48
48

48
48

IN
IN

ODD_RX_DP
ODD_RX_DN

L3
M3

SATA0_RX_DP
SATA0_RX_DN

SATA0_TX_DP
SATA0_TX_DN

N1
M1

ODD_TX_DP
ODD_TX_DN

OUT
OUT

48
48

U2

SATA_RBIAS

1
10K
402

1
10K
402

2

[PAGE_TITLE=SB,

ETHERNET

1

R1C8

2

X02047-012

+ AUDIO

1
10K
402

374
1%
CH
402

1
10K
402

+ SATA]

5%
CH

R2B15 2

1

I2S_MCLK

OUT

41

I2S_BCLK

OUT

28

41
41
41

I2S_SD

5%
CH

47
402

N4
P4

.1UF
10%
6.3V
X5R
402

47
402

R2B12

I2S_WS_R

HDD_RX_DP
HDD_RX_DN

C1C9

R2B13

I2S_BCLK_R

IN
IN

1

5%
CH

47
402

5%
CH

47
402

I2S_MCLK_R

48
48

SATA_RBIAS

40

E2

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

R2B14

IN

39

OUT

5%
CH

33
402

106

OUT

28

I2S_WS

OUT

28

SB_SPDIF_OUT

OUT

28

5%
CH

R2N12 2
5%
CH

R2N11

2

5%
CH

R2N10 2
5%
CH

R1B3

2

5%
CH

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
36/82

REV
1.0

CR-37

:

@FALCON_LIB.FALCON(SCH_1):PAGE37

SB,

STANDBY POWER + DECOUPLING
U2C1

5 of

6

SB VERSION

V_1P8STBY

FB2P4
1
120
0.2A
0.5
DCR

C2R5

4.7UF
10%
6.3V
X5R
805

2

V_AVDD_USB

FB
603

V_AVSS_USB

1

C2P47
2.2UF
10%
6.3V
X5R
603

2
1

ST2P3

2

1
2

C2P43

V_CMPAVDD18_USB

.1UF
10%
6.3V
X5R
402

V_CMPAVSS18_USB
V_VDD18_USB

SHORT

FB2P3
1

2
FB
603

120
0.2A
0.5
DCR

1
2

ST2P2

1

2

1

C2P46
2.2UF
10%
6.3V
X5R
603

2

C2P42

.1UF
10%
6.3V
X5R
402

V_CMPAVSS33_USB
V_VDD33_USB

SHORT

AB13
AA13

AVDD_USB
AVSS_USB

Y13
W13

CMPAVDD18_USB
CMPAVSS18_USB

V13
V12
V11
V10
V9
V8
V7
Y6
W6
V6

VDD18_USB<9>
VDD18_USB<8>
VDD18_USB<7>
VDD18_USB<6>
VDD18_USB<5>
VDD18_USB<4>
VDD18_USB<3>
VDD18_USB<2>
VDD18_USB<1>
VDD18_USB<0>

Y14
W14

CMPAVDD33_USB
CMPAVSS33_USB

V17
V16
V15
V14

VDD33_USB<3>
VDD33_USB<2>
VDD33_USB<1>
VDD33_USB<0>

FB2R1
1

1
2

C2R3

2
FB
603

120
0.5A
0.2DCR

1

4.7UF
10%
6.3V
X5R
805

C2P45

10UF
20%
6.3V
X5R
805

2

1
2

C2P41
.1UF
10%
6.3V
X5R
402

1
2

C2P2
.1UF
10%
6.3V
X5R
402

1
2

C2P3
.1UF
10%
6.3V
X5R
402

V_3P3STBY
37

FB2P5
1

C2R6

FB
603

1
2

1

VDD18_AUX<9>
VDD18_AUX<8>
VDD18_AUX<7>
VDD18_AUX<6>
VDD18_AUX<5>
VDD18_AUX<4>
VDD18_AUX<3>
VDD18_AUX<2>
VDD18_AUX<1>
VDD18_AUX<0>

J18
H18
G18
J15
H15
R14
H14
R12
P12
R9

VDD33_AUX<14>
VDD33_AUX<13>
VDD33_AUX<12>
VDD33_AUX<11>
VDD33_AUX<10>
VDD33_AUX<9>
VDD33_AUX<8>
VDD33_AUX<7>
VDD33_AUX<6>
VDD33_AUX<5>
VDD33_AUX<4>
VDD33_AUX<3>
VDD33_AUX<2>
VDD33_AUX<1>
VDD33_AUX<0>

V19
D19
V18
F18
E18
E17
D17
E16
E15
W5
V5
U5
W4
V4
U4

VSS_USB<25>
VSS_USB<24>
VSS_USB<23>
VSS_USB<22>
VSS_USB<21>
VSS_USB<20>
VSS_USB<19>
VSS_USB<18>
VSS_USB<17>
VSS_USB<16>
VSS_USB<15>
VSS_USB<14>
VSS_USB<13>
VSS_USB<12>
VSS_USB<11>
VSS_USB<10>
VSS_USB<9>
VSS_USB<8>
VSS_USB<7>
VSS_USB<6>
VSS_USB<5>
VSS_USB<4>
VSS_USB<3>
VSS_USB<2>
VSS_USB<1>
VSS_USB<0>

SB BALLS V18 AND V19 ARE IN THE
LOWER RIGHT HAND OF THE CHIP
THEY HAVE BEEN ISOLATED
FOR BETTER POWER ROUTING
V_CMPAVDD33_USB

37

IN

V_3P3STBY

Y19
W19
AB18
AA18
Y17
W17
AB16
AA16
Y15
W15
AB14
AA14
AB12
AA12
Y11
W11
AB10
AA10
Y9
W9
AB8
AA8
Y7
W7
AB6
AA6

V_1P8STBY

1
2

C2P38
.1UF
10%
6.3V
X5R
402

C2P37
.1UF
10%
6.3V
X5R
402

X02047-012

C2P23
.1UF
10%
6.3V
X5R
402

C2P24
.1UF
10%
6.3V
X5R
402

V_3P3STBY

2

120
0.2A
0.5
DCR

4.7UF
10%
6.3V
X5R
805

V_CMPAVDD33_USB

OUT

V_1P8STBY

IC
106

ST2P4

2

C2P48
2.2UF
10%
6.3V
X5R
603

1
2

C2P44

.1UF
10%
6.3V
X5R
402

1
2

C2P6

C2N1

.1UF
10%
6.3V
X5R
402

.1UF
10%
6.3V
X5R
402

C2P5
.1UF
10%
6.3V
X5R
402

SHORT

FB2P1
1

C2P8

120
0.2A
0.5
DCR

4.7UF
10%
6.3V
X5R
805

[PAGE_TITLE=SB,

2
FB
603

1
2

C2P34
2.2UF
10%
6.3V
X5R
603

1
2

C2P35
.1UF
10%
6.3V
X5R
402

STANDBY POWER + DECOUPLING]

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
37/82

REV
1.0

CR-38

:

@FALCON_LIB.FALCON(SCH_1):PAGE38

V_SBPCIE

V_1P8
1

R2C1

0
603
STUFF

THIS

V_1P8

2

U2C1

5%
CH

6 of
SB VERSION

WHEN NOT USING

V_SBPCIE

REGULATOR

V_SBPCIE
FB2P2
1

1
2

C3P3

0.5

2

V_AVSS_PEX

FB
603

120
0.2A
DCR

4.7UF
10%
6.3V
X5R
805

V_AVDD_PEX

1
2

ST2P1

1

2

1

C2P27

2.2UF
10%
6.3V
X5R
603

2

C2P26

V_VDD_PEX_FB

0.01UF
10%
16V
X7R
402

SHORT

R2P17
5%
CH

0
603

1
2

1

C2P10
4.7UF
10%
6.3V
X5R
805

2

1

C2P32
.1UF
10%
6.3V
X5R
402

2

C2P31
0.01UF
10%
16V
X7R
402

V_1P8
FB1P2
1
2

C1P2
4.7UF
10%
6.3V
X5R
805

1
2

C1P7

1
120
0.2A
0.5
DCR

4.7UF
10%
6.3V
X5R
805

2
FB
603

V_AVDD1_SATA
V_AVSS1_SATA

1

C1P5
2.2UF
10%
6.3V
X5R
603

2
ST1P2

1

1

2

C1P6

V_AVDD0_SATA

.1UF
10%
6.3V
X5R
402

2

V_AVSS0_SATA
V_CMPAVDD_SATA
V_CMPAVSS_SATA
V_VDD_SATA

SHORT

FB1P1
1

2

120
0.2A
0.5
DCR

FB
603

1
2

ST1P1

1

2

1

C1P3
2.2UF
10%
6.3V
X5R
603

2

C1P4
.1UF
10%
6.3V
X5R
402

SHORT

FB1P4
1
120
0.2A
0.5
DCR

2
FB
603

1
2

ST1P3

1

2

1

C1P10
2.2UF
10%
6.3V
X5R
603

2

C1P11

.1UF
10%
6.3V
X5R
402

L19
L20

AVDD_PEX
AVSS_PEX

T18
R18
P18
N18
M18

VDD_PEX<4>
VDD_PEX<3>
VDD_PEX<2>
VDD_PEX<1>
VDD_PEX<0>

U22
T22
R22
M22
K22
U21
P21
N21
M21
K21
T20
R20
P20
T19
N19
M19

VSS_PEX<15>
VSS_PEX<14>
VSS_PEX<13>
VSS_PEX<12>
VSS_PEX<11>
VSS_PEX<10>
VSS_PEX<9>
VSS_PEX<8>
VSS_PEX<7>
VSS_PEX<6>
VSS_PEX<5>
VSS_PEX<4>
VSS_PEX<3>
VSS_PEX<2>
VSS_PEX<1>
VSS_PEX<0>

J3
J2

AVDD1_SATA
AVSS1_SATA

H1
H2

AVDD0_SATA
AVSS0_SATA

U1
T1

CMPAVDD_SATA
CMPAVSS_SATA

T5
R5
P5
N5
M5
L5

VDD_SATA<5>
VDD_SATA<4>
VDD_SATA<3>
VDD_SATA<2>
VDD_SATA<1>
VDD_SATA<0>

T4
R4
M4
L4
K4
J4
T3
R3
P3
N3
K3
T2
N2
M2
L2
K2
R1
P1
L1

VSS_SATA<18>
VSS_SATA<17>
VSS_SATA<16>
VSS_SATA<15>
VSS_SATA<14>
VSS_SATA<13>
VSS_SATA<12>
VSS_SATA<11>
VSS_SATA<10>
VSS_SATA<9>
VSS_SATA<8>
VSS_SATA<7>
VSS_SATA<6>
VSS_SATA<5>
VSS_SATA<4>
VSS_SATA<3>
VSS_SATA<2>
VSS_SATA<1>
VSS_SATA<0>

SHORT

FB1P3
1
120
0.5A
0.2DCR

2
FB
603

1
2

[PAGE_TITLE=SB,

C1P8
10UF
20%
6.3V
X5R
805

MAIN

1
2

C2P52
.1UF
10%
6.3V
X5R
402

1
2

IC

6
106
VDD18<17>
VDD18<16>
VDD18<15>
VDD18<14>
VDD18<13>
VDD18<12>
VDD18<11>
VDD18<10>
VDD18<9>
VDD18<8>
VDD18<7>
VDD18<6>
VDD18<5>
VDD18<4>
VDD18<3>
VDD18<2>
VDD18<1>
VDD18<0>

U19
U18
R15
P15
M15
M14
J12
H12
R11
J11
H11
M9
H9
R8
P8
M8
J8
H8

VDD33<13>
VDD33<12>
VDD33<11>
VDD33<10>
VDD33<9>
VDD33<8>
VDD33<7>
VDD33<6>
VDD33<5>
VDD33<4>
VDD33<3>
VDD33<2>
VDD33<1>
VDD33<0>

E14
E13
E12
E11
E10
E9
D8
D7
D6
G5
D5
F4
E4
D4

VSS<41>
VSS<40>
VSS<39>
VSS<38>
VSS<37>
VSS<36>
VSS<35>
VSS<34>
VSS<33>
VSS<32>
VSS<31>
VSS<30>
VSS<29>
VSS<28>
VSS<27>
VSS<26>
VSS<25>
VSS<24>
VSS<23>
VSS<22>
VSS<21>
VSS<20>
VSS<19>
VSS<18>
VSS<17>
VSS<16>
VSS<15>
VSS<14>
VSS<13>
VSS<12>
VSS<11>
VSS<10>
VSS<9>
VSS<8>
VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

N15
L15
K15
P14
N14
L14
K14
J14
R13
P13
N13
M13
L13
K13
J13
H13
N12
M12
L12
K12
P11
N11
M11
L11
K11
R10
P10
N10
M10
L10
K10
J10
H10
P9
N9
L9
K9
J9
N8
L8
K8
A15

V_1P8

1
2

C2P22

.1UF
10%
6.3V
X5R
402

1
2

C2P21

.1UF
10%
6.3V
X5R
402

1

C2P16

.1UF
10%
6.3V
X5R
402

2

1

1

C2P28

.1UF
10%
6.3V
X5R
402

2

1

C2P30

.1UF
10%
6.3V
X5R
402

2

1

C2P17

.1UF
10%
6.3V
X5R
402

2

2

C2P15

.1UF
10%
6.3V
X5R
402

1
2

C2P33

.1UF
10%
6.3V
X5R
402

1
2

C2P29

.1UF
10%
6.3V
X5R
402

V_3P3
V_1P8

C2P39

1

C2P20

1UF
10%
16V
X7R
603

1UF
10%
16V
X7R
603

C1D2

4.7UF
10%
6.3V
X5R
805

2

V_3P3

1
2

C2P13

.1UF
10%
6.3V
X5R
402

1
2

C2P12

.1UF
10%
6.3V
X5R
402

1
2

C2P14

.1UF
10%
6.3V
X5R
402

1
2

C2P11
.1UF
10%
6.3V
X5R
402

1

C2P9

2

.1UF
10%
6.3V
X5R
402

V_3P3

C2P4
1UF
10%
16V
X7R
603

1
2

C2P1
4.7UF
10%
6.3V
X5R
805

C1P1
.1UF
10%
6.3V
X5R
402

X02047-012

POWER + DECOUPLING]

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
38/82

REV
1.0

CR-39

:

@FALCON_LIB.FALCON(SCH_1):PAGE39

N:
N:

123.8
OHM TERMINATION REQUIRED FOR ICS
100 OHM TERMINATION REQUIRED FOR BROADCOM
ENET_RX_DP

40

BI

45

1
39

R1A4

V_ENET

IN

1
2

R1B7

IC
ICS1893BF

ENET_RST_N

IN

2

R1C1
10K
5%
CH
402

1

36
36

39

40

36

IN
IN

MII_MDC_CLK_OUT
2

V_ENET

R1B11

1.5K
402

1

1%
CH

36
36

MII_RX_CLK
MII_RXDV
MII_RXER

34
32
35

RXCLK
RXDV
RXER

36
36
36
36

40
40
40
40

OUT
OUT
OUT
OUT

MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0

28
29
30
31

RXD<3>
RXD<2>
RXD<1>
RXD<0>

MII_TX_CLK
MII_TXEN

37
38

TXCLK
TXEN

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

42
41
40
39

TXD<3>
TXD<2>
TXD<1>
TXD<0>

27
26

MDC
MDIO

43
44

COL
CRS

10

AMDIX_EN

20
19

100TCSR
10TCSR

40
36

OUT
IN

36
36
36
36

IN
IN
IN
IN

40
40

MII_COL
MII_CRS

OUT
OUT
R1N4

100
402

V_ENET

2

R1N1

9.53K
402

RESET_N*

OUT
OUT
OUT

ENET_AMDIX_EN

IN

23
40
40
40

2

39

REF_IN
REF_OUT

36
36
36

MII_MDIO

BI

47
46

1

5%
EMPTY

1

ENET_100BIAS

R1B6

VDD<7>
VDD<6>
VDD<5>
VDD<4>
VDD<3>
VDD<2>
VDD<1>
VDD<0>

48
45
33
14
7
24
22
18

TP_AP
TP_AN

12
13

TP_BP
TP_BN

16
15

2

10K
5%
CH
402

2

10/100

9

VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>

36
25
21
17
11
5
2

R1N2

1

1.58K
1%
CH
402

45

10/100
PIN
INDICATION
ETHERNET

61.9
1%
CH
402

ENET_RX_DN

BI

40

45

ENET_TX_DP

BI

40

45

R1A1

1

10K
5%
CH
402

2

10K
5%
CH
402

1

2
10K
5%
CH
402

ENET_TX_DP_R

1

R1M2
ENET_LINK_N

1

R1N5

2

OUT

40

45

1
10K
5%
CH
402

61.9
1%
CH
402

R1B4

2

R1N6

1

45

OUT

2

R1B5

2

1K
5%
CH
402

ENET_TX_DN_R

R1A2

EMPTY FOR BROADCOM
STUFF FOR ICS

ENET_10_100_OUT

0
5%
CH
603

1

AMDIX_EN HAS INTERNAL PULLUP
AUTO MDIX IS ON BY DEFAULT

2K
1%
CH
402

1

40

OUT

ENET_P2LI_R

2

R1N3

ENET_RX_DN_R

1

R1N7

1

0
5%
CH
603

1

2

X800188-002

DB1N3

2

332
1%
EMPTY
402

8
6
4
3
1

P4RD
P3TD
P2LI
P1CL
P0AC

2

STUFF FOR BROADCOM
EMPTY FOR ICS
R1B13

R1A3
ENET_ACT_N

ENET_10BIAS

1%
CH

2

33

ENET_REF_CLK_OUT

45

OUT

ENET_P1CL

1

DB1N4

R1M1
ENET_POAC_R

1

1

U1B2

ENET_RX_DP_R

1

ENET_P4RD

IN

2

ENET_P3TD

27

ENET_CLK

1K
5%
CH
402

61.9
1%
CH
402

2

IS FOR OUTPUT
OF CONNECTION SPEED

61.9
1%
CH
402

ENET_TX_DN

BI

40

45

ADDRESS="00001"

V_3P3
FB1B1
1
60
0.5A

2
0.1DCR
603

1 C1A5
2

[PAGE_TITLE=SB

OUT,

100UF
20%
16V
ELEC
RDL

ETHERNET]

V_ENET

2
1

C1B1

10UF
20%
6.3V
X5R
805

C1N1
.1UF
10%
6.3V
X5R
402

C1N4
.1UF
10%
6.3V
X5R
402

C1N5

.1UF
10%
6.3V
X5R
402

C1N3
.1UF
10%
6.3V
X5R
402

C1N9
.1UF
10%
6.3V
X5R
402

C1N11
.1UF
10%
6.3V
X5R
402

C1N2
.1UF
10%
6.3V
X5R
402

OUT

39

40

45

C1N10
.1UF
10%
6.3V
X5R
402

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
39/82

REV
1.0

CR-40

:

@FALCON_LIB.FALCON(SCH_1):PAGE40

BDCM PHY
V_1P8
FB1N1
2

2

27

1

DB1N1
39

IN

V_ENET

R1B12

2
36

39

OUT

4.7K
5%
EMPTY
402

MII_RXD0

36

10

RESET_N

20
19
21

RXC
RX_DV/TEST0
RX_ER/TEST1

36
36
36

39
39
39

OUT
OUT
OUT

MII_RXD3
MII_RXD2
MII_RXD1

15
16
17
18

RXD3/ISOLATE
RXD2/F100
RXD1/ANEN
RXD0/PHYAD0

MII_TX_CLK
MII_TXEN

23
24

TXC
TX_EN

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

28
27
26
25

TXD3
TXD2
TXD1
TXD0

39
36

IN

OUT
IN
IN
IN
IN
IN

MII_MDC_CLK_OUT
MII_MDIO

IN
BI
39
39

OUT
OUT

MII_COL
MII_CRS

ENET_AVDD
1
2

[PAGE_TITLE=XDK,

DEBUG LEDS,

BDCM PHY]

C1N6

.1UF
10%
6.3V
EMPTY
402

2

40

C1N14

.1UF
10%
6.3V
EMPTY
402

EMPTY
BCM5241

ENET_RST_N

36
36

40

ENET_REF_CLK2_OUT

1

XTALI2
XTALO2

MII_RX_CLK
MII_RXDV
MII_RXER

36
36
36
36

36

U1B1

1
2

OUT
OUT
OUT

36

39

2

39
39
39

IN

C1N7

10UF
20%
6.3V
EMPTY
805

C1N8

36
36
36

33

1

1

4.7UF
10%
6.3V
EMPTY
805

ENET_CLK

IN

OUT

EMPTY
603

14
13

MDC_CLK_OUT
MDIO

29
30

COL/ENERGYDET
CRS/LOWPWR0

31
32

REGVDDIN
REGVDDOUT

X801554-002

OVDD2
OVDD1
AVDD

22
9

V_ENET

7
12
11

ENET_LINK_N
ENET_ACT_N

TDP
TDN

3
4

RDP
RDN

6
5

RDAC

8

LINK#
ACT#

GND

39

IN

ENET_AVDD

40

IN
OUT
OUT

39
39

45
45

ENET_RX_DP
ENET_RX_DN

OUT
OUT

39
39

45
45

ENET_TX_DP
ENET_TX_DN

OUT
OUT

39
39

45
45

ENET_RDAC

1

ENET_AVDD

1

60
0.5A
0.1DCR

33

1

R1N8
LCC32

2

1.27K
1%
EMPTY
402

DRAWING
FALCON_FABD
Tue May 08 18:24:20

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
40/82

REV
1.0

CR-41

:

@FALCON_LIB.FALCON(SCH_1):PAGE41

V_12P0

V_3P3
R2B1

1

1

0
603

R2B6

2

4.7UF
10%
16V
X5R
1206

AUD_VDD

5%
CH

1
2

C2B11
4.7UF
10%
6.3V
X5R
805

1

2

10UF

2

AUD_AC_R

0.1UF
10%
25V
X7R
603

1

R2B3

1

FB2B2
1

AUD_CLAMP_R

2
0.7DCR
603

1K
0.2A

5%
CH

2

C2B7

R2B5

C2B5
.1UF
10%
6.3V
X5R
402

U2B1

1K
402

20% 16V
TANT
1206

AUD_VAA

5%
CH

C2A7

2

FTP FT2M1

1

1

0
603

FTP FT2N1

2

C2B10

1

IC

1

PGB0010603
603
EG2B2
X801161-001
EMPTY

10K
5%
CH
402

2
1

C2B3
470PF
5%
50V
X7R
402

2

XDAC

33

IN

FTP

1

IN
IN
IN
IN

I2S_MCLK
I2S_BCLK
I2S_SD
I2S_WS

AUD_RST_N
AUD_DCAP

1

2

1K
5%
CH
402

C2B1

10UF
20%
6.3V
X5R
805

C2B6
.1UF
10%
6.3V
X5R
402

MCLK
BCLK
SD
WS

5
12
11

NC
PDN
DVREF

1

AVDD

9

VOUTR
VOUTL

6
10

AVREF

8

AGND

AUD_VOUTL

C2B4

X02238-003

C2B8
10UF
20%
6.3V
X5R
805

PGB0010603
603
EG2B1
X801161-001
EMPTY

C2B9
10UF
1
2

2

2
1K
402

1

R2B2

1

3

AUD_CLAMP_C

Q2N1
1

V_3P3STBY
1

R2N23 2
5%
CH

MMBT3906
XSTR

2
1K
402

R2N2

1

AUD_CLAMP_B2

2

1K
0.2A

CR2M2
2

470PF
5%
50V
X7R
402

FB2B1
1

AUD_CLAMP_L

5%
CH

MBT3904

AUD_CLAMP

C2B2

AUD_AC_L

20% 16V
TANT
1206

4.7K
402

44

R2B4

10K
5%
CH
402

1

IN

OUT

2

1

34

44

7

.1UF
10%
6.3V
X5R
402

FTP

OUT

AUD_L_OUT

AUD_ACAP

DGND

FT2P1

AUD_R_OUT
AUD_VOUTR

2

R2N3

DVDD

13
4
3
2

1

FT2N2

36
36
36
36

14

3

0.7DCR
603

6
2

5

5%
CH

4

1

AUD_CLAMP_B3

2

R2N1

1K
402

XSTR

1

5%
CH

AUD_CLAMP_B1

1

R2N22

2

[PAGE_TITLE=SB

OUT,

AUDIO]

1K
5%
CH
402

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
41/82

REV
1.0

FLSH_DATA1

CR-42

:

@FALCON_LIB.FALCON(SCH_1):PAGE42

N:
N:

FLSH_DATA0
0
1
0

8MB

16MB

1

32MB

64MB

RETAIL=16MB
XDK=64MB

V_3P3STBY

1

1

R2D7

FT1R3
FT1R4
FT1R5
FT2R3
FT2R4
FT2R5
FT2R6
FT2R7

FTP
FTP
FTP
FTP
FTP
FTP
FTP
FTP

1
1
1
1
1
1
1
1

2

10K
5%
CH
402

1

R2D6

2

10K
5%
CH
402

1

R1E2
10K
5%
CH
402

2

2

1

C2E6
4.7UF
10%
6.3V
X5R
805

2

1

C2E5

.1UF
10%
6.3V
X5R
402

2

IN

FLSH_DATA<7..0>

.1UF
10%
6.3V
X5R
402

STUFFED AT CONFIG LEVEL
UPDATE TO RECENT PART NO#

U2E1

IC
NAND FLASH
RDY

1
35

N:
N:

C2R11

FTP FT1T1

7
6
5
4
3
2
1
0

1

1

R2D8

2

10K
5%
EMPTY
402

1

R2D5

2

10K
5%
EMPTY
402

1

R2D4

2

10K
5%
CH
402

1

R2D3

2

10K
5%
CH
402

1

R2D1

2

10K
5%
CH
402

1

R1D4

2

10K
5%
CH
402

1

R1D3

2

10K
5%
CH
402

R1D2

2

10K
5%
CH
402

35
35
35
35
35
35

IN
IN
IN
IN
IN
IN

FLSH_CE_N
FLSH_RE_N
FLSH_WE_N
FLSH_WP_N
FLSH_ALE
FLSH_CLE

37
12

VCC1
VCC0

44
43
42
41
32
31
30
29

DATA<7>
DATA<6>
DATA<5>
DATA<4>
DATA<3>
DATA<2>
DATA<1>
DATA<0>

9
8
18
19
17
16

CE_N*
RE_N*
WE_N*
WP_N*
ALE
CLE

6
36
13

VSS/NC
VSS1
VSS0

NC<27>
NC<26>
NC<25>
NC<24>
NC<23>
NC<22>
NC<21>
NC<20>
NC<19>
NC<18>
NC<17>
NC<16>
NC<15>
NC<14>
NC<13>
NC<12>
NC<11>
NC<10>
NC<9>
NC<8>
NC<7>
NC<6>
NC<5>
NC<4>
NC<3>
NC<2>
NC<1>
NC<0>

X802184-001

[PAGE_TITLE=SB

OUT,

FLASH]

FLSH_READY

7
38
48
47
46
45
40
39
35
34
33
28
27
26
25
24
23
22
21
20
15
14
11
10
5
4
3
2
1

FLSH_NC38

2

R2D2

0
402

OUT

35

1

5%
EMPTY

TSOP

DRAWING
FALCON_FABD
Tue May 08 18:24:17

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
42/82

REV
1.0

CR-43

:

@FALCON_LIB.FALCON(SCH_1):PAGE43

V_3P3STBY
BINDING

BUTTON

FAN CONTROL
1

V_12P0
R5V3

SWITCH
TH
SW5G1
THR

2

4
3

1
2

10K
5%
CH
402

R5V2

2

BINDSW_N_R

10K
402

1

OUT

FAN1_Q1_C

34

IN

FAN1_OUT

1

R1G4

1
2

C4P14
2700PF
10%
50V
X7R
402

1

10K
5%
CH
402

1

2

R1G3

2

EJECTSW_N_R

1

EJECTSW_N

5%
CH

10K
402

34

OUT

48

X02246-002

1

100
5%
CH
402

R4P2

2

1%
CH

V_3P3STBY

C3A9

TILT

SWITCH,

ALPS

1

2

1
2

TILTSW_N_R

30.1K
1%
CH
402

FAN1_FDBK

2

11K
1%
CH
402

2

R2G3

1

TILTSW_N

5%
CH

OUT

34

IR
TILT

SWITCH,

SOLICO

SM
SW2G2
SM

4
3

28

OUT

1

10K
5%
CH
402

10K
402

X800550-003

CONN

R3A2

R2G2

2

4
3

1UF
10%
16V
X7R
603

1

1

SW2G1
SM

J3A2
1X3HDR
1
2
3

V_FAN1

R3A7

5.11K
402

EMPTY

D3A1
1N4148
SOT23
DIO

R3M8

FAN1_FDBK_R

2

4
3

3

FAN1_Q1_E

2

SW1G1
THR

MJD210
XSTR

MMBT2222
XSTR

2

1

TH

Q3M1

3

Q3M2

V_3P3STBY

SWITCH

1

3
28

BUTTON

1

1%
CH
2

BINDSW_N

5%
CH

X02246-002

ODD EJECT

R3M9

2
5.11K
402

MODULE
V_3P3STBY

N: X800550-003
HOLDS ALL THREE TILT
SWITCHES
TMEC ONLY HAS 3 PINS WHICH REQUIRES A DIFFERENT
UNIQUE PART NUMBER TO HOLD THE SYMBOL NAME
N: BOM MUST CALL OUT X800550-003
WITH QTY 1 AND
LIST ALL THREE REF DES.
FACTORY CHOOSES FROM THERE

V_IR

1

1
2

C2V1

4.7UF
10%
6.3V
X5R
805

X800550-003
U1G1

IC

2

1
49.9
402

R2V1
1%
CH

TILT
EMPTY

SWITCH,

SW2G3
TH

3

TMEC

2

C2V2

R2N7

.1UF
10%
6.3V
X5R
402

1

IR
VCC
DATA
GND
ME2
ME1

2

3
1
2
5
4

10K
5%
CH
402

IR_DATA

OUT

34

X803473-002

1
2

X813350-001

[PAGE_TITLE=CONN,

FAN + INFRARED

+ SWITCHES]

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
43/82

REV
1.0

CR-44

:

@FALCON_LIB.FALCON(SCH_1):PAGE44

L3A3
1

1
1

C3A6
62PF
5%
50V
NPO
402

2

75PF
5%
50V
NPO
402

28

IN

1

VID_DACB_OUT

IND
1210

C3A5

4

THRMSTR
1206

1

C2M5

C2A1

4.7UF
10%
6.3V
X5R
805

470PF
5%
50V
X7R
402

2

C3A2
75PF
5%
50V
NPO
402

75
1%
CH
402

1

2

1

1

C3A4

2

1

C3A1
75PF
5%
50V
NPO
402

33

33

1

WSS_CNTL1

IN

R2A6

5.36K
402

WSS_CNTL0

IN

1

2

1%
CH

R2A7

4.75K
402

1%
CH

R2A8

IND
1210

62PF
5%
50V
NPO
402

2

44

OUT

CR2A1

3

MBT3904

3

DIO
SOT363
BAV99

CR3A1

75
1%
CH
402

2

1

R3M3 2

1

VID_VSYNC_OUT_R

49.9
402

CVBS(COMP)

HDTV

SCART

VGA

Y

G

G

PR

R

R

PB

PB

B

B

CVBS

N/A

CVBS

CVBS

VID_DACB_OUT
VID_DACB_RET

8
6

VID_DACC_OUT
VID_DACC_RET

7
5

VID_DACD_OUT
VID_DACD_RET

44

IN

VID_DACD_OUT

44

IN

VID_HSYNC_OUT

11
9

VID_HSYNC_OUT
VID_HSYNC_RET

44

IN

VID_VSYNC_OUT

12
10

VID_VSYNC_OUT
VID_VSYNC_RET

25

SPDIF

41

IN

AUD_R_OUT

15
13

AUD_R_OUT
AUD_R_RET

IN

AUD_L_OUT

16
14

AUD_L_OUT
AUD_L_RET

1

17
19

WSS_CNTL
SCART_RGB

2

R2A5
5%
CH

5%
CH

1K
402

WSS_CNTL_OUT

2
1

10K
402

R2A4 2

1%
CH

CONN

VID_DACC_OUT

WSS_CNTL_OUT_R

1

44

C2A8

CONNECTOR

EXT_PWR_ON

30

EXT_PWR_ON_N

OUT

58

34

44

DDC_CLK
DDC_DATA

21
23

HDMI_DDC_CLK
HDMI_DDC_DATA

BI
BI

28
28

34
34

29
29

AV_MODE2
AV_MODE1
AV_MODE0

28
24
20

AV_MODE2
AV_MODE1
AV_MODE0

OUT
OUT
OUT

34
34
34

44
44
44

26
22
18

GND<2>
GND<1>
GND<0>

34
33
32
31

SHIELD<3>
SHIELD<2>
SHIELD<1>
SHIELD<0>
MTGB<8-1>
MTGA<8-1>

X806743-001

75PF
5%
50V
NPO
402

75PF
5%
50V
NPO
402

VID_VSYNC_OUT

1%
CH

33

44

OUT

SCART_RGB

IN

2

R2N19 1

10K
402

2
SCART_RGB_R

1

TH

58

3

44

5%
CH

OUT

1
33
402

44
44
44
44

IN
IN
IN
IN

EXT_PWR_ON_N
AV_MODE2
AV_MODE1
AV_MODE0

2

1

R2M9 2
5%
CH

1
2

1

R2A1

2

C2M4

0.01UF
10%
16V
X7R
402

10K
5%
CH
402

C2A3
470PF
5%
50V
X7R
402

1

R2M6

2

1
2

LAYOUT:PLACE

10K
5%
CH
402

C2M3
470PF
5%
50V
X7R
402

1

R2M4

2

1
2

10K
5%
CH
402

C2M2

470PF
5%
50V
X7R
402

R2N20

2

1
2

10K
5%
CH
402

C2N3
470PF
5%
50V
X7R
402

CLOSE TO CONNECTOR
EMI CAPS

1

CR3M2
2

AVIP]

1%
CH

1

Q2N3

10K
402

49.9
402

VID_HSYNC_OUT

V_3P3STBY

MMBT3906
XSTR

5%
CH

2 R2M10 1

IN

BAV99
DIO

28

R3M2 2

1

VID_HSYNC_OUT_R

6

DIO
SOT363
BAV99

4

5

CVBS(COMP)

IN

C3A8

V_3P3STBY

[PAGE_TITLE=[CONN,

D

IN

SCART_RGB_OUT_R

CR3M2

V_3P3STBY

N/A

44

XSTR

1

3

IN

N/A

44

V_3P3

28

C

VID_DACA_OUT
VID_DACA_RET

41

4

301
402

OUT

PR

3
1

2

1%
CH

R2A9 2
2

62PF
5%
50V
NPO
402

1

VID_DACD_OUT

SDTV

IND
1210

C3A7

4

2

5

V_3P3

.27UH
0.45A
NA

1

R3A9

2

Y

C(CHROMA)

4
2

2

1

1

VID_DACD_DP

Y(LUMA)

N/A

VID_DACB_OUT

6

5

L3A4
IN

N/A

B

VID_DACA_OUT

WSS_CNTL_B

WSS_CNTL_E

28

ADVANCED

SCART_RGB_OUT

R3A6

VID_DACC_OUT

2

DIO
SOT363
BAV99

6

.27UH
0.45A
NA

1

CR3A1
2

V_3P3

2

1.82K
402

1

VID_DACC_DP

A

IN

44

L3A1
IN

STANDARD

XENON AVIP
V_AVIP
V_AVIP_RET

29
27

V_12P0

28

DAC

J3A1

V_3P3
1

62PF
5%
50V
NPO
402

2

44

OUT

2

DIO
SOT363
BAV99

3
CR3A2

R3A3

2

5

V_3P3

.27UH
0.45A
NA

1
75
1%
CH
402

2

C2A6
22PF
5%
50V
NPO
402

29

V_AVIP

2

2
1

VID_DACB_DP

2

HANA_SPDIF_OUT

L3A2
IN

RT2M1

1.1A
0.21DCR

C3A3

1

28

OUT

V_5P0

44

D2A1

1

2

OUT

3

1

75
1%
CH
402

VID_DACA_OUT

IND
1210

1

R3A4

CR3A2

6

1

2

2

V_3P3

2

.27UH
0.45A
NA

DIO
SOT23S
BAV99

VID_DACA_DP

IN

DIO
SOT363
BAV99

28

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
44/82

REV
1.0

CR-45

:

@FALCON_LIB.FALCON(SCH_1):PAGE45

V_5P0DUAL
RT1B1
2

V_EXPPORT

IN

D1A2

BI

EXPPORT_DN

1

3

35

BI

EXPPORT_DP

4

BAV99
SOT23S
DIO

2

1

470PF
5%
50V
X7R
402

2
1

1

C1M2
4.7UF
10%
6.3V
X5R
805

OUT

45

FTP FT1N2

EXPPORT_DN_CM

3

EXPPORT_DP_CM

D1A1

X801560-001

1

2
3

R1B1

1

5%
CH

BAV99
SOT23S
DIO

PGB0010603
603

PGB0010603
603

EG1A2

EG1A1

EMPTY

EMPTY

2

0
603

2 ELEC
RDL

C1A3

1

EMPTY

CMCHOKE

2

2

35

1 C2A4

220UF
20%
10V

5%
CH

NA
SM
L1B1

THRMSTR
1206

2

R1B2
0
603

V_EXPPORT

1

1.1A
0.21DCR

1

45

J1A1

CONN

XENON RJ45/USB

IN

ARGON_NTX
D1B1

45

IN

V_EXPPORT

2

470PF
5%
50V
X7R
402

1

1
BAV99
SOT23S
DIO
39

IN

V_ENET

VBUS
DD+
GND

16

OMNI

C1A4

2
3

12
13
14
15

1
0
402

1
0
402

R1M3 2
5%
EMPTY

R1A5

2

5%
EMPTY

IN
IN

ENET_P2LI_R

40

39
39

IN
IN

ENET_POAC_R

40

39
39

40

39

IN

ENET_TX_DP

40

39

IN

ENET_TX_DN

40

39

IN

ENET_RX_DP

40

39

IN

ENET_RX_DN

ENET_LINK_N
ENET_ACT_N
ENET_TX_CT

ENET_RX_CT

C1M1
.1UF
10%
6.3V
X5R
402

1
2

LED_LEFT_A
LED_LEFT_C

3
4

LED_RIGHT_A
LED_RIGHT_C

11
10
7

XFMER2_P
XFMER2_C
XFMER2_N

9
6
5

XFMER1_P
XFMER1_C
XFMER1_N

8

CAP

C1A2
.1UF
10%
6.3V
X5R
402

20
19
18
21
17

COMBO

EMI4
EMI3
EMI2
EMI1
ME1
X806148-001

[PAGE_TITLE=CONN,

RJ45

+ USB COMBO]

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
45/82

REV
1.0

CR-46

:

@FALCON_LIB.FALCON(SCH_1):PAGE46

V_MEMPORT1

RT2G1

RT8G1

2
1

1.1A
0.21DCR

V_GAMEPORT2

THRMSTR
2
1206

1

2

1 C9G2

C9G5

4.7UF
10%
6.3V
X5R
805

2

220UF
20%
10V
ELEC
RDL

1

470PF
5%
50V
X7R
402

2
PGB0010603
603

BI

1

D9G1

X801560-001

4

2

DIO

GAMEPORT2_DP_CM

V_5P0DUAL

GAMEPORT1_DN_CM

RT8G2
V_GAMEPORT1

1

4.7UF
10%
6.3V
X5R
805

2

1 C9G3
220UF
20%
10V
ELEC
RDL

2

1

EG4G1

GAMEPORT1_DP_CM

C9G6

PGB0010603
603

DIO

GAMEPORT2_DN_CM

1

THRMSTR
1206
2

MEMPORT2_DP_CM

PGB0010603
603

EG9G1

J4G2

C9G4
470PF
5%
50V
X7R
402

1

2
1
2
3
4

5%
CH

CONN

VBUS
DD+
GND

5
6
7
8

VBUS
DD+
GND

9
10

EMI1
EMI2

11
12

ME1
ME2

X800245-003

R3G4
0
603

1 C2G2

2

2

1

220UF
20%
10V
ELEC
RDL

C3V5
470PF
5%
50V
X7R
402

2

C2G3
4.7UF
10%
6.3V
X5R
805

1

5%
CH

NA
SM
L2G1
35

BI

MEMPORT1_DN

1

35

BI

MEMPORT1_DP

4

EMPTY

CMCHOKE

2

1
2
3
4
5

GND
VBUS
DD+
GND

6
7
8
9
10

GND
VBUS
DD+
GND

14
13
12
11

EMI4
EMI3
EMI2
EMI1

15
16
17
18

ME4
ME3
ME2
ME1

MEMPORT1_DN_CM

3

MTGA<8-1>
MTGB<8-1>
MTGC<8-1>

MEMPORT1_DP_CM

X800059-001

V_5P0DUAL
R2G5

3

5%
CH

L9V1

BI

GAMEPORT1_DN

4

35

BI

GAMEPORT1_DP

1

CMCHOKE

3

1

35

EMPTY
D9V1

R9V1

[PAGE_TITLE=CONN,

5%
CH

1

2

2
3

0
603

1

EG2G1

DIO

DIO

V_MPORT

V_5P0
PGB0010603
603

EG9V1
2
X801560-001

EG3G1

EMPTY
BAV99
SOT23S
DIO

EMPTY

5%
CH

TH

PGB0010603
603

EG9V2

1

NA
SM

PGB0010603
603

2

0
603

1

R9V2

0
603

2

D9V2

PGB0010603
603

2

1

X801560-001

2

CONN

XENON MU

R4G4
0
603

TH
J9G1

BAV99
SOT23S
DIO

1

3

XENON GAME
CONN

5%
CH

1.1A
0.21DCR

MEMPORT2_DP

MEMPORT2_DN_CM

EG4G2

3

R9G1

2

BI

2

PGB0010603
603

2

0
603

35

CMCHOKE

EMPTY

2

1

1

2

3

1

GAMEPORT2_DP

BAV99
SOT23S
DIO

EMPTY

CMCHOKE

4

GAMEPORT2_DN

MEMPORT2_DN

X801560-001

2

35

BI

BI

1

1

NA
SM
35

35

EMPTY

3

5%
CH

L9G1

C5G6
4.7UF
10%
6.3V
X5R
805

1

NA
SM

2

R9G2 2

2

2

C4V6
470PF
5%
50V
X7R
402

5%
CH

L4G1

2

D9G2

220UF
20%
10V
ELEC
RDL

R4G5
0
603

EMPTY

V_5P0DUAL

60

V_MEMPORT2
1

1 C5G4

C9G1

EG9G2

0
603

FB5G1
2
1
120
FB
0.5A
603
0.2DCR

1
THRMSTR
1206

1.1A
0.21DCR

1

2

1

OUT

V_MPORT

V_5P0DUAL

2

C1U2
1.0UF
10%
16V
X7R
805

U1F2

IC
NCP1117

3

IN

1

ADJUST/GND

OUT

2

1
1

X800499-001

2

C1F6
0.1UF
10%
25V
X7R
603

FTP FT1V1

1 C1F4

100UF
20%
16V

2 ELEC
RDL

1
BAV99
SOT23S
DIO

MEMORY PORTS + GAME PORTS]

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
46/82

REV
1.0

CR-47

:

@FALCON_LIB.FALCON(SCH_1):PAGE47

XDK BOARD MAPPING
DEBUG BOARD MAPPING

59

IN

1
1
1

CPU_DBGSEL_XDK<0..69>
N:CONNECT TO CPU
DEBUG OUT

FTP FT6U11
FTP FT6U9
FTP FT6U10

CPU_DBGSEL_DEBUG<0..69>

IN

N:CONNECT TO CPU
DEBUG OUT

52
53
54
55

DBG_CPU_LINKTRAINED
DBG_CPU_SECURE_SYS
DBG_CPU_PLL_LOCK
DBG_CPU_TST_CLK

1
1
1
1

56
57
58
59
60
61
62
63

DBG_CPU_POST_OUT0
DBG_CPU_POST_OUT1
DBG_CPU_POST_OUT2
DBG_CPU_POST_OUT3
DBG_CPU_POST_OUT4
DBG_CPU_POST_OUT5
DBG_CPU_POST_OUT6
DBG_CPU_POST_OUT7

1
1
1
1
1
1
1
1

DB6E1
DB6E2
DB6E3
DB6E4

FTP
FTP
FTP
FTP
FTP
FTP
FTP
FTP

FT6U8
FT6U2
FT6U3
FT6U4
FT6U5
FT6U6
FT6U7
FT6U1

V_5P0STBY
V_5P0STBY

V_12P0

1

1

1 C1D11

10K
5%
CH
402

2
10K
402

VREG_V5P0_SEL_C

R1R5

ELEC
2 RDL

10K
5%
CH
402

2
1

3
4

VREG_V5P0_SEL_PGATE

5%
CH

2

CR1D1

IN

VREG_V5P0_SEL
FT1R1

FTP

1

1
4.7K
402

R1D6

2

1
VREG_V5P0_SEL_B1

VREG_V5P0_SEL_B2

5%
CH

IC
SI4501DY

D<3>
D<2>
D<1>
D<0>

V_5P0

C1R3
.22UF
10%
6.3V
X5R
402

2
1

2

XSTR

1

5
8
7
6

1

1

2

4.7K
5%
CH
402

R1G1

1K
5%
CH
402

FTP FT1R2

1

R1G2

G1
S1
X801132-002

R1D5

1

V_5P0DUAL

S2
G2

VREG_V5P0_SEL_NGATE

MBT3904
34

U1R1

20
1%
CH
1206

2

BLEEDER_C1

2

220UF
20%
10V

R1R3

R1V2

2

20
1%
CH
1206

BLEEDER_C2

R1R2

3

Q1G2

1

VREG_5P0_SEL

VREG_5P0_SEL
NGATE/PGATE

V_5P0DUAL

3
27

[PAGE_TITLE=[MISC,

HIGH

LOW

V_5P0STBY

LOW

HIGH

V_5P0

V_5P0

DUAL,

IN

SMC_RST_N

DEBUG MAPPING]

2
10K
402

R1V1
5%
CH

1

BLEEDER_B

MMBT2222
XSTR

2

Q1V1

1

MMBT2222
XSTR
2

DRAWING
FALCON_FABD
Tue May 08 18:24:20

2007

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

CPU_DBG_TERM<0..69>

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

OUT

PAGE
47/82

REV
1.0

CR-48

:

@FALCON_LIB.FALCON(SCH_1):PAGE48

V_5P0
D1E4
2
3
36

HDD_TX_DP

IN

C1E4

1

2

1

10%
0.01UF
16V
X7R
402

BAV99
SOT23S
DIO

HDD_TX_DP_C

HDD SATA AND POWER

HDD_TX_DN_C

36

HDD_TX_DN

IN

D1E3

C1E3

1

2

J1E1

2

0.01UF
10%
16V
X7R
402

1
2
3
4
5
6
7

3
1
BAV99
SOT23S
DIO

V_5P0

1

10%
0.01UF
16V
X7R
402

BAV99
SOT23S
DIO

1

1

PGB0010603
603

PGB0010603
603

EG1E3

EG1E2

EG1E1

EMPTY

EMPTY

EMPTY

EMPTY

HDD_RX_DN_C

HDD_RX_DP_C

36

HDD_RX_DP

OUT

1

C1E1

2

2

2

1.5A
0.11DCR

3

1

1

2

1 C1E5

1

2

100UF
20%
16V
ELEC
RDL

ODD POWER DECOUPLING

ODD_TX_DP_C

36

IN

ODD_TX_DN

1

C1C5

2

V_12P0

OUT

ODD_RX_DN

1

C1C4

2

ODD_RX_DN_C

0.01UF
10%
16V
X7R
402
36

OUT

ODD_RX_DP

1

C1C3

2

1
2
3
4
5
6
7

1 C1C10
100UF
20%
16V
ELEC
RDL

2

470PF
5%
50V
X7R
402

RT1R1
1

1.1A
0.21DCR

C1C14
1UF
10%
16V
X7R
603

C1C13
0.1UF
10%
25V
X7R
603

1 C1C11
2

100UF
20%
16V
ELEC
RDL

C1D6

V_XPOD

THRMSTR
1206

C1T1

V_3P3

V_5P0

470PF
5%
50V
X7R
402

ODD POWER AND CONTROL
CR1D2

1UF
10%
16V
X7R
603

.1UF
10%
6.3V
X5R
402

1

OUT

TRAY_STATUS

1

R1R4

100
402

2

TRAY_STATUS_R

5%
CH

2

100UF
20%
16V
ELEC
RDL

C1D4
1UF
10%
16V
X7R
603

C1D1
1UF
10%
16V
X7R
603

C1D3
.1UF
10%
6.3V
X5R
402

BAV99
SOT23S
EMPTY

J1D1
1
3
5
7
9
11

4
6
8
10
12

V_12P0

1

BAV99
SOT23S
EMPTY

V_3P3

1 C1D9

CONN

ODD + HDD]

2
3

V_5P0

ODD_RX_DP_C

CR1D3

3

8
CONN

V_3P3

C1T2

1UF
10%
16V
X7R
603

C1R1

34

0.01UF
10%
16V
X7R
402

[PAGE_TITLE=CONN,

C1T3

1UF
10%
16V
X7R
603

V_3P3

9

0.01UF
10%
16V
X7R
402

36

C1T4

1UF
10%
16V
X7R
603

2

J1C1
SATA

ODD_TX_DN_C

TH

X800351-002

C1T5

2

0.01UF
10%
16V
X7R
402

ME1
ME2

V_HDD

THRMSTR
1812

V_5P0DUAL

ODD_TX_DP

EMI1
EMI2

17
18

MTGA<8-1>
MTGB<8-1>

ODD SATA
IN

15
16

RT1U1

BAV99
SOT23S
DIO

36

GND
GND
GND
V_HDD
V_HDD
V_HDD
V_XPOD

V_5P0
D1E1

0.01UF
10%
16V
X7R
402

C1C6

8
9
10
11
12
13
14

2

2

PGB0010603
603

EG1E4

2

1

PGB0010603
603

2

HDD_RX_DN

OUT

3

2

36

1

2
C1E2

1

D1E2

CONN
XENON HDD
CONN

GND
D+
DGND
DD+
GND

DRAWING
FALCON_FABD
Tue May 08 18:24:20

2007

MICROSOFT
CONFIDENTIAL

EJECTSW_N
TRAY_OPEN
1
2

IN
IN

43
34

C1R4
75PF
5%
50V
NPO
402

PROJECT NAME
FALCON_RETAIL

PAGE
48/82

REV
1.0

:

@FALCON_LIB.FALCON(SCH_1):PAGE49

V_3P3STBY

V_12P0
1
1 C6G5

2

2

1

100UF
20%
16V
ELEC
RDL

C6G2

470PF
5%
50V
X7R
402

2

R6G7

1
0
603

2

34

IN

5%
CH

1500UF
20%
16V
ALUM
RDL

L6G1

BI

35

BI

ARGONPORT_DP

1

2

R8A1

EMPTY

2

3

X801560-001

1
2

R6G8

0
603

1

C6G3

470PF
5%
50V
EMPTY
402

2

2

C6G4

470PF
5%
50V
EMPTY
402

ARGON_DN_CM
ARGON_DP_CM

5%
CH

USE LC NETWORK FOR USB 1.1
USE USB CHOKE FOR USB 2.0

V_3P3STBY
1

R3N7
10K
5%
CH
402

2
34

IN

PWRSW_N

2

R3N6

10K
402

5%
CH

34
34

ARGON_DATA
ARGON_CLK

BI
BI

2

1

PWRSW_N_R

2
1

1

C6V15
470PF
5%
50V
X7R
402

C6V11
470PF
5%
50V
X7R
402

2
1

VCC
DD+
GND

5
6
7
8
9

SPARE
C_DATA
C_CLK
GND
NTX
EMI1
EMI2

12
13

ME1
ME2

2

2

BI

1

C8A1
.1UF
10%
6.3V
X5R
402

2

2

C8A2

470PF
5%
50V
EMPTY
402

0
603

5%
EMPTY

L6G2

EMPTY

CMCHOKE

3

BI

MEMPORT3_DN_ARGON

1

2

1 C5B7

100UF
20%
16V
ELEC
RDL

[PAGE_TITLE=CONN,

V12P0
V12P0
V12P0

7

PSU_EN

8

VSB5P0

9
10
13
14

EMI1
EMI2
EMI3
EMI4

11
12

ME1
ME2

X811487-001

1 C8B1

1

2

2

100UF
20%
16V
ELEC
RDL

TH

C9A4
470PF
5%
50V
X7R
402

V_5P0STBY

V_12P0

1

1

470PF
5%
50V
X7R
402

R8B5

MEMPORT3_DP_ARGON_CM

V_12P0

R7B2

2.2K
5%
CH
402

2.2K
5%
CH
402

2

2
549
402

R8N1

2
2.2K
402

R6G38 2
5%
EMPTY

ARGON + POWER SUPPLY]

27

IN

ANA_V12P0_PWRGD

2
2.2K
402

R8A4

1

5%
CH

R8A3

BLEEDER_V12P0_B1

3
1

BLEEDER_V12P0_B2

Q8N1

BCP51
XSTR
2 4

BLEEDER_V12P0_LOAD

1

R7N3
Q8B4

MMBT2222
XSTR

2

10
1%
CH
805

1

R7N1

2

10
1%
CH
805

1

R7N4

2

10
1%
CH
805

R7N2

2

10
1%
CH
805

2

Q8B5

1

1

1%
CH

1

1

MEMPORT3_DN_ARGON_CM

3

56
603

4
5
6

X800095-001

C6V10

X801560-001

1

GND
GND
GND

FTP FT8N1

3
60

1
2
3

DB8N1

1

2

CONN
XENON PWR

MTGA<8-1>
MTGB<8-1>

1

V_5P0STBY

2

4

J9A1

R6G37 2

1

MEMPORT3_DP_ARGON

C9A2

0.1UF
10%
25V
X7R
603

2

PSU_V12P0_EN_R

1

NA
SM
60

1

C9A6

0.1UF
10%
25V
X7R
603

1

5%
CH

10K
5%
CH
402

XENON RF
CONN

1
2
3
4

10
11

0.1UF
10%
25V
X7R
603

DB8M1
DB8M2
DB8M3

TH
CONN

J6G1

2

1

C9A5

R8A2

100
402

1

CMCHOKE

1

2

1

BLEEDER_V12P0_C1

35

4

C9A1
0.1UF
10%
25V
X7R
603

PSU_V12P0_EN

NA
SM
ARGONPORT_DN

1

1 C9B1

1
1
1

FTP FT9N1

BLEEDER_V12P0_C2

CR-49

MMBT2222
XSTR

2

1

5%
CH

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
49/82

REV
1.0

CR-50

:

@FALCON_LIB.FALCON(SCH_1):PAGE50

4
4

IN

CPU_VREG_APS5

IN

CPU_VREG_APS4

IN

CPU_VREG_APS3

4

IN

CPU_VREG_APS2

4

IN

CPU_VREG_APS1

IN

CPU_VREG_APS0

4

4

R7E3
0
402

5

5%
CH

R7E5
0
402

0
402

R7E2

4

5%
CH

5%
CH

0
402

V_GPUCORE

R7E1

3

1

R7E4
0
402

5%
CH

5%
CH

R7T6
10K
5%
CH
402

1

R7E6
1K
402

1

2

2

0

5%
CH

2

5

10K
5%
EMPTY
402

10K
5%
EMPTY
402

2

10K
5%
EMPTY
402

2

10K
5%
CH
402

1

10K
5%
EMPTY
402

2

10K
5%
CH
402

2

2

10K
5%
CH
402

0

VREG_CPU_VID<5..0>

R7T12
10K
5%
CH
402

N:CPU

INPUT

2

2

N:GPU

2

C9B2
4.7UF
10%
16V
X5R
1206

1.6UH
10A
NA

2

V_VREG_CPU

IND
TH

C9C4

C9C1

1500UF
20%
16V
ALUM
RDL

C9E3

1500UF
20%
16V
ALUM
RDL

C9D2

1500UF
20%
16V
ALUM
RDL

1500UF
20%
16V
ALUM
RDL

1

C9B4

4.7UF
10%
16V
EMPTY
1206

2

1
2

1
2

1

OUTPUT FILTER

52

4.7UF
10%
16V
EMPTY
1206

FILTER

C8B2

2

1.6UH
10A
NA

IND
TH

4.7UF
10%
16V
X5R
1206

V_VREG_GPU
1 C6B3

1 C7B3

1

2

2

2

1500UF
20%
16V
ALUM
RDL

1500UF
20%
16V
ALUM
RDL

C8B4
4.7UF
10%
16V
X5R
1206

1
2

C6B5

4.7UF
10%
16V
X5R
1206

1

OUT
1

C6N2

2

4.7UF
10%
16V
X5R
1206

2

C7B4
4.7UF
10%
16V
X5R
1206

1

53

4.7UF
10%
16V
X5R
1206

2

DB8P2

V_GPUCORE

FTP FT7T9

N:GPU

1

OUTPUT FILTER

FTP FT5R2

1 C8C2

1 C8E3

1 C8E1

1 C8F1

1 C8E2

1 C8D1

1 C8C1

1 C8D4

1 C7C2

1 C7C1

1 C6C3

1 C7C3

1 C6C2

1 C6C1

1 C5C8

1 C5C9

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2 EMPTY
8X8

820UF
20%
6.3V
EMPTY
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
EMPTY
RDL

820UF
20%
6.3V
ALUM
RDL
1

[PAGE_TITLE=VREGS,

INPUT

+ OUTPUT FILTERS]

54

C7N3

DB8P1

1
V_CPUCORE

OUT

51

C9C3

1

N:CPU

INPUT

L8B1
1

1

51

10K
5%
EMPTY
402

FILTER

L9B1
1

OUT

R7T16

V_12P0
V_12P0

WATERNOSE=011100=1.1625V
DD1.0 REQUIRES VID0 RC
DD2.0
NO STUFF RC
LOKI=100001=1.05V

1

R7T14

10K
5%
CH
402

R7T9

1

1

R7T15

2

10K
5%
EMPTY
402

N:
N:
N:
N:

1

R7T5

2

1

R7T11

2

1

R7T7

3

1

R7T13

1

R7T8

4

1

2

1

R7T4

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
6.3V
ALUM
RDL

820UF
20%
2.5V
EMPTY
8X8

820UF
20%
2.5V

FTP FT7U4

DRAWING
FALCON_FABD
Tue May 08 18:24:18

2007

MICROSOFT
CONFIDENTIAL

PROJECT NAME
FALCON_RETAIL

PAGE
50/82

REV
1.0


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